參數(shù)資料
型號： MC56F8000RM
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 66/124頁
文件大?。?/td> 1880K
代理商： MC56F8000RM
56F8013 Technical Data, Rev. 2
66
Freescale Semiconductor
Preliminary
6.3.1.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 8–6
6.3.1.9
OnCE Enable (ONCEEBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.3.1.10 Software Reset (SWRST)—Bit 4
Writing 1 to this field will cause the part to reset.
6.3.1.11 Stop Disable (STOP_DISABLE[1:0])—Bits 3–2
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.12 Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
6.3.2
This register is updated upon any system reset and indicates the cause of the most recent reset. It also
controls whether the COP reset vector or regular reset vector in the vector table is used. This register is
asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is
synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only
one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the
highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR,
COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the
external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted.
SIM Reset Status Register (SIM_RSTAT)
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
0
0
0
0
0
0
0
0
0
0
SWR
COPR
EXTR
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
相關PDF資料
PDF描述
MC56F8014 16-bit Digital Signal Controllers
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MC56F8155VFG 16-bit Hybrid Controllers
MC56F8323 16-bit Hybrid Controller(16位混合控制器)
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