參數(shù)資料
型號： MC56F8000RM
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 76/124頁
文件大?。?/td> 1880K
代理商： MC56F8000RM
56F8013 Technical Data, Rev. 2
76
Freescale Semiconductor
Preliminary
6.3.10.1 Reserved—Bits 15—2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.10.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.4 Clock Generation Overview
The SIM uses master clocks from the OCCS module to produce the peripheral and system (core and
memory) clocks. The HS_PERF clock input from OCCS operates at three times the system and peripheral
bus rate, or a maximum of 96MHz. The SYS_CLK_x2 clock input from OCCS operates at two times the
system and peripheral bus rate, or a maximum of 64MHz. Peripheral and system clocks are generated at a
maximum of 32MHz by dividing the SYS_CLK_x2 clock by two and gating it with appropriate power
mode and clock gating controls. The PWM and TIMER peripheral clocks can optionally be generated at
three times the normal rate at a maximum of 96MHz. These clocks are generated by gating the HS_PERF
clock with appropriate power mode and clock gating controls.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC).
When selected, the relaxation oscillator can be operated at full speed (8MHz), standby speed (400kHz
using ROSB), or powered down (using ROPD). An 8MHz MSTR_OSC can be multiplied to 196MHz
using the PLL and postscaled to provide a variety of high speed clock rates. Either the postscaled PLL
output or MSTR_OSC signal can be selected to produce the master clocks to the SIM. When the PLL is
not selected, the HS_PERF clock is disabled and the SYS_CLK_x2 clock is MSTR_OSC.
In combination with the OCCS module, the SIM provides power modes (see
Section 6.5
), clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to
provide flexible
control of clocking and power utilization. The SIM’s clock enable controls can be used to disable
individual clocks when not needed. The clock rate controls enable the high speed clocking option for the
Timer channels and PWM but require the PLL to be on and selected. Refer to the
56F8300 Peripheral
User Manual
for further details.
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
ISAL[21:6]
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
相關PDF資料
PDF描述
MC56F8014 16-bit Digital Signal Controllers
MC56F8014VFAE 16-bit Digital Signal Controllers
MC56F8155VFG 16-bit Hybrid Controllers
MC56F8323 16-bit Hybrid Controller(16位混合控制器)
MC56F8345 16-bit Hybrid Controller(16位混合控制器)
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