參數(shù)資料
型號(hào)： MC56F8000RM
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁數(shù)： 65/124頁
文件大?。?/td> 1880K
代理商： MC56F8000RM
Register Descriptions
56F8013 Technical Data, Rev. 2
Freescale Semiconductor
Preliminary
65
6.3.1.1
This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode.
Timer Channel 3 Stop Disable (TC3_SD)—Bit 15
0 = Timer Channel 3 disabled in Stop mode
1 = Timer Channel 3 enabled in Stop mode
6.3.1.2
This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.
Timer Channel 2 Stop Disable (TC2_SD)—Bit 14
0 = Timer Channel 2 disabled in Stop mode
1 = Timer Channel 2 enabled in Stop mode
6.3.1.3
This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.
Timer Channel 1 Stop Disable (TC1_SD)—Bit 13
0 = Timer Channel 1 disabled in Stop mode
1 = Timer Channel 1 enabled in Stop mode
6.3.1.4
This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.
Timer Channel 0 Stop Disable (TC0_SD)—Bit 12
0 = Timer Channel 0 disabled in Stop mode
1 = Timer Channel 0 enabled in Stop mode
6.3.1.5
This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in
LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is
in Sleep mode and using Stop mode to reduce power consumption.
SCI Stop Disable (SCI_SD)—Bit 11
0 = SCI disabled in Stop mode
1 = SCI enabled in Stop mode
6.3.1.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bit 10
6.3.1.7
This bit selects the input of Timer Channel 3 to be from the PWM or GPIO.
Timer Channel 3 Input (TC3_INP)—Bit 9
0 = Timer Channel 3 Input from PWM reload_sync signal
1 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields
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