參數(shù)資料
型號(hào): MAX7000B
廠商: Altera Corporation
英文描述: Programmable Logic Device
中文描述: 可編程邏輯器件
文件頁(yè)數(shù): 6/66頁(yè)
文件大?。?/td> 421K
代理商: MAX7000B
6
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Figure 1. MAX 7000B Device Block Diagram
Note:
(1)
EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten
output enables.
Logic Array Blocks
The MAX 7000B device architecture is based on the linking of
high-performance LABs. LABs consist of 16 macrocell arrays, as shown in
Figure 1
. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
6 or 10
6 or 10
INPUT/GCLRn
6 or 10 Output Enables (1)
6 or 10 Output Enables (1)
16
36
36
16
I/O
Control
Block
LAB C
LAB D
I/O
Control
Block
6 or 10
16
36
36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6 or 10
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
2 to 16
Macrocells
17 to 32
Macrocells
33 to 48
Macrocells
49 to 64
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