參數(shù)資料
型號: MAX7000B
廠商: Altera Corporation
英文描述: Programmable Logic Device
中文描述: 可編程邏輯器件
文件頁數(shù): 48/66頁
文件大?。?/td> 421K
代理商: MAX7000B
48
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Table 28. EPM7256B Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-7
-10
Min
Max
Min
Max
Min
Max
t
IN
t
IO
t
FIN
t
FIND
Input pad and buffer delay
0.4
0.4
1.5
1.5
0.6
0.6
2.5
1.5
0.8
0.8
3.1
1.5
ns
ns
ns
ns
I/O input pad and buffer delay
Fast input delay
Programmable delay adder for
fast input
t
SEXP
t
PEXP
t
LAD
t
LAC
t
IOE
t
OD1
Shared expander delay
1.5
0.4
1.7
1.5
0.1
0.9
2.3
0.6
2.5
2.2
0.2
1.4
3.0
0.8
3.3
2.9
0.3
1.9
ns
ns
ns
ns
ns
ns
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
slow slew rate = off
V
CCIO
= 3.3 V
Output buffer and pad delay
slow slew rate = on
V
CCIO
= 2.5 V or 3.3 V
Output buffer enable delay
slow slew rate = off
V
CCIO
= 3.3 V
Output buffer enable delay
slow slew rate = on
V
CCIO
= 2.5 V or 3.3 V
Output buffer disable delay
C1 = 35 pF
t
OD3
C1 = 35 pF
5.9
6.4
6.9
ns
t
ZX1
C1 = 35 pF
2.2
3.3
4.5
ns
t
ZX3
C1 = 35 pF
7.2
8.3
9.5
ns
t
XZ
t
SU
t
H
t
FSU
t
FH
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
C1 = 5 pF
2.2
3.3
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register setup time
1.2
0.6
0.8
1.2
1.8
1.0
1.1
1.4
2.5
1.3
1.1
1.4
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
0.7
0.3
1.5
1.5
1.3
1.0
1.0
1.7
2.0
1.0
0.4
2.3
2.2
2.1
1.6
1.6
2.6
3.0
1.3
0.5
3.0
2.9
2.7
2.1
2.1
3.3
4.0
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
(2)
Low-power adder
(4)
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