參數(shù)資料
型號(hào): MAX7000B
廠商: Altera Corporation
英文描述: Programmable Logic Device
中文描述: 可編程邏輯器件
文件頁(yè)數(shù): 26/66頁(yè)
文件大?。?/td> 421K
代理商: MAX7000B
26
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Two inverters implement the bus-hold circuitry in a loop that weakly
drives back to the I/O pin in user mode.
Figure 10
shows a block diagram of the bus-hold circuit.
Figure 10. Bus-Hold Circuit
PCI
Compatibility
MAX 7000B devices are compatible with PCI applications as well as all
3.3-V electrical specifications in the
PCI Local Bus Specification
Revision 2.2
except for the clamp diode. While having multiple clamp
diodes on a signal trace may be redundant, designers can add an external
clamp diode to meet the specification.
Table 13
shows the MAX 7000B
device speed grades that meet the PCI timing specifications.
Note:
(1)
The EPM7256B and EPM7512B devices in a -5 speed grade meet all PCI timing
specifications for 66-MHz operation except the Input Setup Time to CLK—Bused
Signal parameter. However, these devices are within 1 ns of that parameter.
EPM7256B and EPM7512B devices meet all other 66-MHz PCI timing
specifications.
I/O
R
BH
Bus Hold Circuit
Drive to
VCCIO level
Table 13. MAX 7000B Device Speed Grades that Meet PCI Timing
Specifications
Device
Specification
33-MHz PCI
66-MHz PCI
EPM7032B
EPM7064B
EPM7128B
EPM7256B
EPM7512B
All speed grades
All speed grades
All speed grades
All speed grades
All speed grades
-3
-3
-4
-5
(1)
-5
(1)
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