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參數(shù)資料
| 型號： | MAX7000B |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device |
| 中文描述： | 可編程邏輯器件 |
| 文件頁數(shù)： | 16/66頁 |
| 文件大?。?/td> | 421K |
| 代理商： | MAX7000B |
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Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000B device through the
TDI
input pin. Data is
shifted out through the
TDO
output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP
. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1 ms.
2.
Check ID
. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase
. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program
. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify
. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP
. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1 ms.
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (
TCK
) frequency and the
number of
TCK
cycles to shift instructions, address, and data into the
device.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX7000S | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| MAX700C/D | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX700C/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX700CPA | 功能描述:監(jiān)控電路 Integrated Circuits (ICs) RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX700CPA+ | 功能描述:監(jiān)控電路 Power-Supply Monitor w/Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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