參數(shù)資料
型號: MAX7000B
廠商: Altera Corporation
英文描述: Programmable Logic Device
中文描述: 可編程邏輯器件
文件頁數(shù): 21/66頁
文件大?。?/td> 421K
代理商: MAX7000B
Altera Corporation
21
MAX 7000B Programmable Logic Device Data Sheet
Figure 8. MAX 7000B JTAG Waveforms
Table 9
shows the JTAG timing parameters and values for MAX 7000B
devices.
Note:
(1)
Timing parameters in this table apply to all V
CCIO
levels.
Table 9. JTAG Timing Parameters & Values for MAX 7000B Devices
Note (1)
Symbol
Parameter
Min
Max
Unit
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK
clock period
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK
clock high time
50
TCK
clock low time
50
JTAG port setup time
20
JTAG port hold time
45
JTAG port clock to output
25
JTAG port high impedance to valid output
25
JTAG port valid output to high impedance
25
Capture register setup time
20
Capture register hold time
45
Update register clock to output
25
Update register high impedance to valid output
25
Update register valid output to high impedance
25
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
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