參數(shù)資料
型號(hào): MAX7000B
廠商: Altera Corporation
英文描述: Programmable Logic Device
中文描述: 可編程邏輯器件
文件頁(yè)數(shù): 33/66頁(yè)
文件大?。?/td> 421K
代理商: MAX7000B
Altera Corporation
33
MAX 7000B Programmable Logic Device Data Sheet
Timing Model
MAX 7000B device timing can be analyzed with the Altera software, with
a variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in
Figure 13
. MAX 7000B
devices have predictable internal delays that enable the designer to
determine the worst-case timing of any design. The Altera software
provides timing simulation, point-to-point delay prediction, and detailed
timing analysis for device-wide performance evaluation.
Figure 13. MAX 7000B Timing Model
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
Figure 14
shows the timing relationship
between internal and external delay parameters.
f
See
Application Note 94 (Understanding MAX 7000 Timing)
for more
information.
Logic Array
Delay
t
LAD
Output
Delay
t
OD1
t
OD3
t
XZ
Z
t
X1
t
ZX2
t
ZX3
t
OD2
Input
Delay
t
IN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
PIA
Delay
t
PIA
Shared
Expander Delay
t
SEXP
Register
Control Delay
t
LAC
t
IC
t
EN
I/O
Delay
t
IO
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Parallel
Expander Delay
t
PEXP
Fast
Input Delay
t
FIN
t
FIN
t
FIND
+
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