參數(shù)資料
型號： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述： 單片微機16位的CMOS（16位單片機）
文件頁數(shù)： 88/158頁
文件大小： 1261K
代理商： M37920FGCHP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
88
In the array chain transfer, the transfer parameters are first read from
the transfer parameter memory and then written into the SAR, DAR,
and TCR. This operations state is called the
“
array state
”
. Figures 83
and 84 show timing diagram examples in the array chain transfer
mode (burst transfer mode). The DMA controller outputs the start ad-
dress of the transfer parameter memory to the address bus, and se-
quentially stores the read data into the SAR, DAR, and TCR.
When the transfer parameters for 1 block are completely stored, the
contents of the TBC are decremented by 1, and then, the first DMA
transfer starts in accordance with the stored parameters. These op-
erations for storing parameters are called
“
array state
”
.
In contrast to the array state, the state in which DMA transfer is ac-
tive is called
“
transfer state
”
. In the transfer state, the same opera-
tions are performed as in the single transfer mode. Each time when
1-transfer-unit data has been transferred, the contents of the TCR
are decremented by 1 in 8-bit transfer or by 2 in 16-bit transfer. Even
when the contents of the TCR become 0, the DMA request bit and
DMA enable bit are not cleared to
“
0
”
and the array state of the next
block starts.
When the contents of the TBC are 0 at the start of the array state,
the entire transfer operation is considered to be completed, and
“
L
”
level is output into pin TC to clear the DMA request bit and DMA en-
able bit and terminate array chain transfer. At the same time, the in-
terrupt request bit of the DMA interrupt control register is set to
“
1
”
.
In the cycle steal transfer at the array chain transfer mode, one array
state and transfer cycle of 1 transfer unit are made by one DMA re-
quest.
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