參數(shù)資料
型號(hào)： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁(yè)數(shù)： 111/158頁(yè)
文件大?。?/td> 1261K
代理商： M37920FGCHP
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111
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
In the clock generating circuit, the basic clock which is used to oper-
ate the CPU and each internal peripheral device is made by a clock
input from pin X
IN
. Figure 111 shows the block diagram of the clock
generating circuit. The clock which is input from the external clock in-
put pin, X
IN
, generates the following;
φ
, which is used to operate the microcomputer
φ
BIU
, which is used to operate the BIU
φ
CPU
, which is used to operate the CPU
φ
is stopped only when the external clock input is disabled by STP
instruction.
φ
BIU
is stopped when to STP or WIT instruction is ex-
ecuted. Also,
φ
CPU
is stopped when STP or WIT instruction is ex-
ecuted or when a CPU wait request is issued by the BIU.
f
1(
φ
)
is the basic clock for internal peripheral devices. This basic clock
is divided furthermore in the divide circuit, as shown in Figure 111,
and some frequency types are generated. Serial I/O communication
and timer B can use any of four clocks (f
2
, f
16
, f
64
, f
512
), respectively.
Timer A can use any of six clocks (f
2
, f
16
, f
64
, f
512,
and f
1(
φ
)
and f
4096
).
“
f
2
”
indicates that this clock is f
1(
φ
)
divided by 2. For operation of the
watchdog timer, refer to section on the watchdog timer.
When the STP instruction is executed,
φ
,
φ
BIU
, and
φ
CPU
stop at the
“
L
”
state.
The STP mode is terminated by acceptance of an interrupt, and the
oscillation is started. Simultaneously, supply of
φ
is started.
When the watchdog timer starts to count down with Wf
32
and the
most significant bit of the watchdog timer is cleared to
“
0
”
, supply of
φ
BIU
and
φ
CPU
is restarted. The count source of the watchdog timer
is back to the count source which was selected before execution of
the STP instruction, and the generated interrupt request is accepted.
When the WIT instruction is executed,
φ
BIU
and
φ
CPU
stops at the
“
L
”
state. However,
φ
is not stopped. Immediately after the interrupt re-
quest is accepted,
φ
BIU
and
φ
CPU
start their operations.
In order to terminate the STP or WIT mode by a non-maskable inter-
rupt, it is necessary to make the interrupt request acceptable before
execution of the STP or WIT instruction. For setting method, refer to
the section on interrupts.
Figure 109 shows a circuit example with an external ceramic reson-
ator or a quartz crystal oscillator. The constants such as capacitance
etc. depend on a resonator. Therefore, for these constants, adopt the
oscillator/resonator manufacturer
’
s recommended values. Figure
110 shows a circuit e example with an external clock source.
Fig. 109 Circuit example with external ceramic resonator or quartz crystal oscillator
Fig. 110 Circuit example with external clock source
X
IN
R
f
X
OUT
R
d
C
IN
C
OUT
X
IN
X
OUT
Left open.
External oscillation circuit
Vcc
Vss
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