參數(shù)資料
型號(hào)： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 79/158頁
文件大?。?/td> 1261K
代理商： M37920FGCHP
79
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Fig. 74 Example of cycle steal transfer
DMAREQ
0
DMA0 request bit
DMA0 enable bit
(CPU) DMA1
(CPU)
(CPU)
The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source
Channel priority : fixed (channel 0 > channel 1)
DMA0
DMA1 DMA0
DMA1
DMA1
DMAREQ
1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
DRAM
(2) Cycle steal transfer mode
When bit 2 of the DMAi
mode register L is set to “1”, the cycle steal
transfer mode is selected. In the cycle steal transfer mode, be sure
to select the edge sense mode.
When a DMA request occurs in the cycle steal transfer mode, the
corresponding DMA request bit is set to “1” as in the burst transfer
mode. When the DMA request from the channel is accepted, DMA
transfer starts. However, the DMA request bit is automatically
cleared to “0” at the start of the first DMA transfer cycle. Therefore, if
there is no DMA request from any channel when 1-transfer-unit data
has been transferred, the DMA controller returns the right to use bus
to the CPU. If there is a DMA request from a channel, the DMA con-
troller continues to use the bus and initiates DMA transfer for the
channel. In the cycle steal transfer mode, the priorities of the chan-
nels are detected at all times to assure that the DMA request from a
channel having the highest priority is accepted to initiate the DMA
transfer execution. The DMA request bit is cleared to “0”, at each
time when 1-transfer-unit data has been transferred. At this time,
however, the DMA enable bit will not be cleared to “0” although the
DMA request bit is cleared to “0” at each transfer of 1 transfer unit.
Therefore, when the DMA request bit is set to “1” next, transfer is re-
sumed at the point of interruption. When the transfer counter
register’s value is “0” in the single transfer, or when both of the trans-
fer counter register’s value and transfer block counter’s value are “0”
in the array chain transfer, the DMA enable bit will be cleared to ”0”
to terminate the whole DMA transfer operation.
Figure 74 shows an example of cycle steal transfer. When pin
DMAREQ
i
’s input level changes from “H” to “L”, the DMA1 request
bit will be set to “1” and the DMA controller will acquire the right to
use bus and initiate DMA transfer. The DMA1 request bit is cleared
to “0” when the channel 1 transfer cycle starts. Therefore, if there is
no DMA transfer request from the other channels, the DMA control-
ler returns the right to use bus to the CPU at the end of 1 transfer
cycle. In the example shown in Figure 74, however, DMA0 transfer
cycle execution continues because the channel 0’s request bit is set
to “1”. When the DMA0 transfer cycle is terminated, the DMA re-
quest bits of all channels are cleared to “0” so that the DMA control-
ler returns the right to use bus to the CPU. When the DMA1 request
bit is set to “1”, only one cycle of transfer operation is performed.
Even if the DMA1 request bit is cleared to “0” at this time, the DMA1
request bit is set to “1” again to perform continuous transfer, as long
as pin DMAREQ
i
’s input level goes “L” before the end of the next
transfer cycle. In the cycle steal transfer, the priorities of individual
channels are detected at the end of each transfer cycle. Therefore, if
the request is issued from channel 0, which has a higher priority than
channel 1, channel 0 transfer is executed first. Furthermore, if a re-
quest to use bus which has a higher priority (for example, a refresh
request from the DRAM controller) is generated, this request takes
the precedence.
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