參數(shù)資料
型號： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 154/158頁
文件大?。?/td> 1261K
代理商： M37920FGCHP
Corrections and
Page
Supplement
ar
Erro
20F8CGP and M37920F
y
Explanation
r
for M37920FxC Dat
asheet (REV.
Correction
A) NO.2
(2/6)
Page 9,
Fig. 1
Fig. 2. Memory map of M37920FCCGP and
M37920FCCHP (Single-chip mode)
g. 3. M
emory
map of
M37920FGCH
P (
S
ingle-chip mode)
Fig. 1. Memory map of M37920FCCGP and
M37920FCCHP (Single-chip mode)
Mem
(Singl
ory m
e-
chi
ap of M
p m
ode)
379
8CHP
(Deleted)
Fi
M37920F
G
C
G
P
and
Fig. 2. Memory map of M37920FGCGP and
M37920FGCHP (Single-chip mode)
Page 10,
Fig. 2
Page 11,
Fig. 4;
address
00
16
, 01
16
000000
16
000001
16
000000
16
000001
16
Reserved area
(Note)
Reserved area
(Note)
b31
b0
DB
Data buff
er
b31
b0
DQ
Data buff
er
Page 18,
Fig. 8
Data buff
er
Temporarity stores data which has been ,
and external areas by the BIU or which is to be
writeen to internal memory, .
Temporarily stores data which has been ,
and external areas by the BIU; or temporarily
stores data which is to be written to internal
memory, .
Page 18,
Table 1
Instruction
queue buffer
Temporarity stores an instruction which .
Temporarily stores an instruction which .
(this contents is published for one page)
ALE
is an addr
ess latch enabl
No
t
e:
The chip select wait contr
select wait contr
o
e
si
gnal.
ol
ler,
by the chip
ller.
(Deleted)
T
of
he f
S
“
i
nal page
election of
p
r
ocessor
m
ode”
Processor mode register 1
1
0
2
4
3
5
6
7
Recovery cycle insert select bit
HOLD input, HLDA output select
bit
0:
(P4
0
and P4
4
function as )
1:
0
0
ALE output select bit
RDY input select bit
Direct page register switch bit
Page 28,
Fig. 12
Processor mode register 1
1
0
2
4
3
5
6
7
Recovery cycle insert select bit
(Notes 2 and 3)
HOLD input, HLDA output
select bit
(Notes 2 to 4)
0:
(P4
3
and P4
4
function as )
1:
0
0
ALE output select bit
(Notes 2
and 3)
RDY input select bit
(Notes 2
to 4)
Direct page register switch bit
(Note 1)
Internal ROM access wait bit
Internal ROM access wait bit
(Note 5)
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