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參數(shù)資料
| 型號(hào)： | M37920FGCHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī)) |
| 中文描述： | 單片微機(jī)16位的CMOS（16位單片機(jī)） |
| 文件頁(yè)數(shù)： | 14/158頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FGCHP |
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M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
MITSUBISHI MICROCOMPUTERS
14
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing mode.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-or-
der 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank regis-
ter (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indi-
rect, direct indirect indexed Y, absolute, absolute bit, absolute in-
dexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3)
The direct page register is a 16-bit register. An addressing mode of
which name includes
‘
direct
’
generates an address of data to be ac-
cessed, regarding the contents of this register as the base address.
The 7900 Series has been expanded direct page registers up to 4
(DPR0 to DPR3), in comparison to the 7700 Series which has the
single direct page register. Accordingly, the 7900 Series
’
s direct ad-
dressing method which uses direct page registers differs from that of
the 7700 Series. However, the conventional direct addressing
method, using only DPR0, is still be selectable, in order to make use
of the 7700 Series software property. For more details, refer to the
section on the direct page.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of
flags to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V, and
N.
The details of each bit of the processor status register are described
below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU af-
ter an arithmetic operation. This flag is also affected by shift and ro-
tate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to
“
1
”
, all interrupts except
watchdog timer, NMI, and software interrupt are disabled. This flag
is set to
“
1
”
automatically when an interrupt is accepted. It can be set
and reset directly with the SEI and CLI instructions or SEP and CLP
instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is
“
0
”
. If it is
“
1
”
, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when data length flag m is
“
0
”
and with
two digits when it is
“
1
”
. Decimal adjust is automatically performed.
(Decimal operation is possible only with the ADC and SBC instruc-
tions.) This flag can be set and reset with the SEP and CLP instruc-
tions.
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