參數(shù)資料
型號： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述： 單片微機16位的CMOS（16位單片機）
文件頁數(shù)： 90/158頁
文件大?。?/td> 1261K
代理商： M37920FGCHP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
90
(4) Link array chain transfer mode
Figure 85 shows the perameter memory map in the link array chain
transfer mode. As shown in this figure, not only the transfer source
’
s
transfer start address, transfer destination
’
s transfer start address,
and number of transfer bytes, but also the start address of the
memory block which contains the next transfer parameters is stored.
In the transfer parameter of the last block, be sure to set
“
000000
16
”
as the start address of the next transfer parameter. For 1-bus cycle
transfer, the external I/O side
’
s parameters are not needed.
In the link array chain transfer, also, the DMAi mode registers L and
H, DMAi control register, and DMAC control registers L and H must
be set up. Into the SAR, write the start address of the memory block
that stores the parameters for the first transfer. This value is then
written into the TPR. Be sure that an even-numbered address is set
to the start address.
Nothing needs to be written in the DAR. Write the value 1 or more
into the TCR. When the DMA enable bit is set to
“
1
“
after completion
of the above setup, DMA transfer becomes enabled.
In the link array chain transfer, the transfer parameters are first read
from the transfer parameter memory and then written into the SAR,
DAR, and TCR. Further, the start address of the memory block that
contains the next parameters has been written into the TPR. In the
link array chain transfer mode, the state so far is referred to as the
array state.
The DMA controller sequentially outputs the transfer parameters to
the address bus, beginning with the start address of the memory
block, storing the transfer parameters. The read data are sequen-
tially stored into the SAR, DAR, and TCR, and then the start address
of the memory block, containing the next parameters, is written into
the TPR. A DMA transfer is made in accordance with the parameters
read from the transfer parameter memory. The transfer state is the
same as in the single transfer mode. The contents of the TCR are
decremented by 1 or 2 each time when 1-transfer-unit data has been
transferred.
Even when the contents of the TCR become 0, the DMA request bit
and DMA enable bit are not cleared to
“
0
”
but the array state starts
again. When the contents of the TPR are 0 at this time, however,
“
L
”
level is output into pin TC to clear the DMA request bit and DMA en-
able bit to
“
0
”
and terminate the link array chain transfer. At the same
timing, the interrupt request bit of the DMA interrupt control register
is set to
“
1
”
.
In the cycle steal transfer at the link array chain transfer mode, one
array state and the transfer cycle of 1 transfer unit are made by one
DMA request.
Figures 86 and 87 show timing diagram examples in the link array
chain transfer mode (burst transfer mode).
Fig. 85 Parameter memory map example in link array chain trans-
fer mode
Transfer source
’
s transfer start address 1
Transfer destination
’
s transfer start address 1
Number of transfer bytes 1
Transfer parameter address 2
Transfer source
’
s transfer start address 4
Transfer destination
’
s transfer start address 4
Number of transfer bytes 4
Transfer parameter address 5
T
Transfer parameter
address 4
Transfer source
’
s transfer start address 3
Transfer destination
’
s transfer start address 3
Number of transfer bytes 3
Transfer parameter address 4
Transfer parameter
address 3
Transfer source
’
s transfer start address 2
Transfer destination
’
s transfer start address 2
Number of transfer bytes 2
Transfer parameter address 3
Transfer parameter
address 2
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