
107
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Fig. 105 Microcomputer internal register
’
s status just after reset (2)
(80
16
)
···
Address
CS
0
control register L
(81
16
)
···
CS
0
control register H
(82
16
)
···
CS
1
control register L
(83
16
)
···
CS
1
control register H
(8C
16
)
···
Area CS
1
start address register
(84
16
)
···
CS
2
control register L
(85
16
)
···
CS
2
control register H
(86
16
)
···
CS
3
control register L
(87
16
)
···
CS
3
control register H
(8A
16
)
···
Area CS
0
start address register
(DC
16
)
···
DMA1 mode register L
(DD
16
)
···
DMA1 mode register H
(DE
16
)
···
DMA1 control register
(EC
16
)
···
DMA2 mode register L
(ED
16
)
···
DMA2 mode register H
(8E
16
)
···
Area CS
2
start address register
(90
16
)
···
Area CS
3
start address register
Notes 1:
The contents of the other registers and RAM are undefined at reset and must be initialized by software.
2:
The status just after reset depends on the voltage level applied to pin MD0.
3:
While Vss level voltage is applied to pin BYTE, these bits are
“
0
”
. While Vcc level voltage is applied to pin BYTE, on the other hand, these
bits are
“
1
”
.
0
0 0 0
0
(A8
16
)
···
DRAM
control register
(B2
16
)
···
DMA0 interrupt control register
0 0 0 0
(B3
16
)
···
DMA1 interrupt control register
0 0 0 0
(B4
16
)
···
DMA2 interrupt control register
(CC
16
)
···
DMA0 mode register L
0 0 0
(CE
16
)
···
DMA0 control register
(A0
16
)
···
Real-time output control register
(AC
16
)
···
CTS/RTS separate select register
(B0
16
)
···
DMAC control register L
0
0
0
0
0
0
0
0
(CD
16
)
···
DMA0 mode register H
(B5
16
)
···
DMA3 interrupt control register
0
0
0 0 0
(EE
16
)
···
DMA2 control register
(FC
16
)
···
DMA3 mode register L
(FD
16
)
···
DMA3 mode register H
(FE
16
)
···
Address
DMA3 control register
0
0 0
0
0
0
0
0
0
0
0
0
1 0
(Note 2)
(Note 3)
1 0
0
1 0 0
0
(Note 3)
1 0
0
1 0 0
0
(Note 3)
1 0
0
1 0 0
0
(Note 3)
1 0
0 0 0
0 0 0 0
0 0 0 0
0
0
0
0
0
0
0
0
0 0 0
0
0 0
0
0
0
0
0
0
0
0
0
0
0 0
0 0 0
0
0 0 1
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0
0
0 0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0 0 0
0
0 0
0
0
0 0
0
0
0 0 0
0
0 0
0
0
0 0 1
0
0 0 0
0
0 0 0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
0
0 0 0
(9E
16
)
···
Flash memory control register
0
0 0
0 0 1
0
0
0 0
0 0
(B1
16
)
···
DMAC control register H
0 0
RESET CIRCUIT
While the power source voltage satisfies the recommended operat-
ing condition, reset state is removed if pin RESET
’
s level returns
from the stabilized
“
L
”
level to the
“
H
”
level. As a result, program ex-
ecution starts from the reset vector address. This reset vector ad-
dress is expressed as shown below:
A
23
to A
16
= 00
16
A
15
to A
8
= Contents at address FFFF
16
A
7
to A
0
= Contents at address FFFE
16
Figures 104 and 105 show the microcomputer internal register
’
s sta-
tus just after reset, and Figure 106 shows an operation example of
the reset circuit. Apply
“
L
”
level voltage to pin RESET for a period (2
μs or more) under the following conditions:
Pin Vcc
’
s level satisfies the recommended operating condition.
Oscillator
’
s operation has been stabilized.
Fig. 106 Operation example of reset circuit (Note that proper evalu-
ation is necessary in the system development stage.)
V
CC
RESET
Power on
V
CC
level
0.2V
CC
level
2
μ
s
Oscillation stabilized
f(X
IN
)
0V
0V
0V