參數(shù)資料
型號： M37920FGCHP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 29/158頁
文件大?。?/td> 1261K
代理商： M37920FGCHP
29
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Microprocessor mode
V
CC
level voltage is applied
10
SFR area
Internal RAM area
External memory area
External memory area
Low-order address (A
0
to A
7
) is output.
Middle-order address (A
8
to A
15
) is output.
Multiplexed address (MA
0
to MA
7
) is
output
(Note 3)
High-order address (A
16
to A
23
) is output.
Multiplexed address (MA
8
to MA
11
) is
output
(Note 3)
Low-order data (D
0
to D
7
, data at even-
numbered address) is input/output.
Low-order data (D
0
to D
7
, data at even-/
odd-numbered address) is input/output.
Low-order data (D
0
to D
7
, data at odd-
numbered address) is input/output.
I/O port pins P2
0
to P2
7
Ready signal RDY is input.
I/O port pin P3
0
(Note 5)
Read signal RD is output
Write signal BLW (write to even-num-
bered address) is output.
Write signal BLW (write to even-/odd-
numbered address) is output.
Write signal BHW (write to odd-num-
bered address) is output.
I/O port pin P3
3
Memory expansion mode
V
SS
level voltage is applied
01
SFR area
Internal RAM area
Internal ROM area
External memory area
Low-order address (A
0
to A
7
) is output.
Middle-order address (A
8
to A
15
) is output.
Multiplexed address (MA
0
to MA
7
) is output
(Note 3)
High-order address (A
16
to A
23
) is output.
Multiplexed address (MA
8
to MA
11
) is out-
put
(Note 3)
Low-order data (D
0
to D
7
, data at even-
numbered address) is input/output.
Low-order data (D
0
to D
7
, data at even-/
odd-numbered address) is input/output.
Low-order data (D
0
to D
7
, data at odd-num-
bered address) is input/output.
I/O port pins P2
0
to P2
7
I/O port pin P3
0
Ready signal RDY is input
(Note 5).
Read signal RD is output.
Write signal BLW (write to even-numbered
address) is output.
Write signal BLW (write to even-/odd-num-
bered address) is output.
Write signal BHW (write to odd-numbered
address) is output.
I/O port pin P3
3
Table 10. Relationship between processor modes, memory area, and port function
Single-chip mode
V
SS
level voltage is applied
Pin MD0
Processor mode
bits
(Note 2)
SFR area
Internal RAM area
Internal ROM area
Other area
Mode
(Note 1)
00
SFR area
Internal RAM area
Internal ROM area
(Do not access.)
I/O port pins P10
0
to P10
7
I/O port pins P11
0
to P11
7
I/O port pins P0
0
to P0
7
I/O port pins P1
0
to P1
7
I/O port pins P2
0
to P2
7
I/O port pin P3
0
I/O port pin P3
1
I/O port pin P3
2
I/O port pin P3
3
M
Port pins P10
0
to P10
7
Port pins P11
0
to P11
7
Port pins P0
0
to P0
7
Port pins
P1
0
to P1
7
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
External data bus
width = 8 bits
Port pins
P2
0
to P2
7
Port pin P3
0
Port pin P3
1
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
External data bus
width = 8 bits
Port pin
P3
2
Port pin
P3
3
Notes 1:
For details of the processor mode setting, see Table 9.
2:
Processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5E
16).
3:
While DRAM space is accessed, the multiplexed address is output.
4:
In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E
16
, 5F
16
), port pins P3
0
, P4
0
to
P4
3
can operate as pins for RDY input, ALE output,
φ
1
output, HLDA output, HOLD input, respectively.
In the microprocessor mode, by the above select bits, the above pins (RDY, ALE,
φ
1
, HLDA, HOLD) can operate as port pins P3
0
, P4
0
to P4
3
, respec-
tively.
5:
In the memory expansion mode, port pin P9
0
can operate as the CS
0
output pin by the CS
0
output select bit of the CS
0
control register L (bit 7 at address 80
16
).
6:
In the memory expansion and microprocessor modes, port pins P9
1
to P9
3
can operate as the CS
1
/CS
2
/CS
3
output pins by the CS
i
output select bits (i =
1 to 3) (bit 7s at addresses 82
16
, 84
16
, 86
16
).
I/O port pin P4
0
I/O port pin P4
1
Clock
φ
1
is output
(Note 4)
.
I/O port pin P4
2
I/O port pin P4
3
I/O port pin P9
0
I/O port pins P9
1
to P9
3
Port pin P4
0
Port pin P4
1
Port pin P4
2
Port pin P4
3
Port pin P9
0
Port pins P9
1
to P9
3
I/O port pin P4
0
Address latch enable signal ALE is output
(Note 4)
.
I/O port pin P4
1
Clock
φ
1
is output
(Note 4)
.
I/O port pin P4
2
Hold acknowledge signa HLDA is output
(Note 4)
.
I/O port pin P4
3
Hold request signal HOLD is input
(Note 4)
.
I/O port pin P9
0
Chip select signal CS
0
is output
(Note 5)
.
I/O port pins P9
1
to P9
3
C
hip select signals CS
1
to CS
3
are output
(Note 6)
.
Address latch enable signal ALE is output.
I/O port pin P4
0
(Note 4)
Clock
φ
1
is output.
I/O port pin P4
1
(Note 4)
Hold acknowledge signal HLDA is output.
I/O port pin P4
2
(Note 4)
Hold request signal HOLD is input.
I/O port pin P4
3
(Note 4)
Chip select signal CS
0
is output.
I/O port pin P9
1
to P9
3
Chip select signals CS
1
to CS
3
are output
(Note 6)
.
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