參數(shù)資料
型號： M37920FGCGP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 78/158頁
文件大小： 1261K
代理商： M37920FGCGP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
78
Fig. 72 Burst transfer example (in edge sense mode)
DMAREQ
0
DMA0 request bit
DMA0 enable bit
DMA1
DMA1
DMA0
Channel 0 entire data transfer
Channel 1 entire data transfer
The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source (edge sense)
Channel priority : fixed (channel 0 > channel 1)
(CPU)
(CPU)
DMAREQ
1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
refresh
Fig. 73 Burst transfer example (in level sense mode)
DMAREQ
0
DMA0 request bit
DMA0 enable bit
(CPU)
DMA1
(CPU)
DMA1
(CPU)
The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source (level sense)
Channel priority : fixed (channel 0 > channel 1)
DMA0
DMAREQ
1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
refresh
When channel 1
’
s DMA transfer is entirely completed, the right to
use bus is once passed to the CPU, and the DMA transfer request
from channel 0 is later accepted at the end of the current bus cycle.
When bit 4 of the DMAi control register is set to
“
1
”
, the level sense
mode is selected. The level sense mode can be used only for the
DMA request from pin DMAREQ
i
. When selecting another source,
be sure to select the edge sense mode.
In the level sense mode, the DMAi request bit is set to
“
1
”
to initiate
the DMA transfer only while pin DMAREQ
i
’
s input level is
“
L
”
. If pin
DMAREQ
i
’
s input level returns to
“
H
”
in the middie of transfer, the
DMA operation is interrupted at the end of the current transfer bus
cycle or next transfer bus cycle so that the right to use bus is re-
turned to the CPU. At this time, the DMA enable bit is not cleared.
When pin DMAREQ
i
’
s input level returns to
“
L
”
, the transfer opera-
tion is resumed at the address which is next to the point of interrup-
tion. In the level sense mode, the DMA request bit varies only with
the input level at pin DMAREQ
i
. Therefore, while pin DMAREQ
i
’
s in-
put level is
“
L
”
, the DMA request bit remains to be
“
1
”
even if the
transfer is completed.
Figure 73 shows a burst transfer example in level sense mode.
When pin DMAREQ
i
’
s input level for channel 1 changes from
“
H
”
to
“
L
”
during CPU operation, the DMA1 request bit will be set to
“
1
”
so
that the DMA controller will acquire the right to use bus and initiate
transfer. When pin DMAREQ
i
’
s input level returns to
“
H
”
, the DMA1
request bit is cleared to
“
0
”
. This causes the DMA transfer operation
to be interrupted and returns the right to use bus to the CPU.
相關(guān)PDF資料
PDF描述
M37920FCCGP Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
M37920FCCHP Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
M37920FGCHP Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
M3802 Single Chip 8 Bits Microcomputer(8位單片機(jī))
M3820 Single Chip 8 Bits Microcomputer(8位單片機(jī))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37920FGCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920S4CGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER
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