參數資料
型號: M37920FGCGP
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述: 單片微機16位的CMOS(16位單片機)
文件頁數: 31/158頁
文件大?。?/td> 1261K
代理商: M37920FGCGP
31
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Chip select wait controller
By the control of the chip select wait controller (CSWC), the chip se-
lect function for the maximum of 4 blocks can be set at the bus ac-
cess to the external area.
Also, by the setting of the CSWC, port pins P9
0
to P9
3
can operate
as chip select output pins (CS
0
to CS
3
).
Figure 14 shows a chip select output waveform example.
This chip select function determines the following items of the chip
select area: start address, address
s block size, wait number, exter-
nal data bus width, RDY control validity, DRAM specification, burst
ROM specification, and recovery cycle insertion validity.
For the external area except for areas CS
0
to CS
3
, the processor
mode registers 0, 1 determine the above items. After reset is re-
moved, when the microcomputer starts it
s operation in the micropro-
cessor mode, area CS
0
is automatically selected.
Table 12 lists the function of areas CS
0
to CS
3
.
Figure 15 shows the bit configuration of the CS
0
/CS
1
/CS
2
/CS
3
con-
trol register Ls. These registers determine the following items of a
device to be connected: wait number, external data bus width (
Note
1:
The external data bus width of area CS
0
is determined by pin
BYTE
s level.), RDY control validity, DRAM space specification
(
Note 2:
For area CS
0
, this function is invalid.), burst ROM access
specification, recovery cycle insertion validity. For DRAM access,
refer to the section on the DRAM controller.
Figure 16 shows the bit configuration of the CS
0
/CS
1
/CS
2
/CS
3
con-
trol register Hs. These registers determine block size of an external
area to be connected. For areas CS
1
and CS
2
, by selecting mode 1
with the area CSk setting mode select bit, an chip select area can be
set to the external area in bank 0.
Figure 17 shows the bit configuration of the area CS
0
/CS
1
/CS
2
/CS
3
start address registers. For details of these addresses
setting, see
Figures 18 to 20.
When area CS
i
is accessed
φ
1
A
23
to A
0
ALE
RD,
When the same area CS
i
is accessed sequentially
φ
1
A
23
to A
0
ALE
RD,
Address + 2
One access
cycle
Address
One access
cycle
Address
CS
i
BLW, BHW
BLW, BHW
One access
cycle
CS
i
Fig. 14 Chip select output waveform example
G
Burst ROM access
For ROM supporting the burst ROM access, the burst ROM access
can be specified. The burst ROM access is valid only when the ex-
ternal data bus width = 16 bits with an instruction prefetched. In the
other cases, the normal access is performed regardless of the con-
tents of the burst ROM access select bit.
Figure 21 shows a waveform example at burst ROM access.
When an instruction is prefetched from the burst ROM, 8 bytes are
fetched starting from an 8-byte boundary (the low-order 3 bits of ad-
dress, A
2
, A
1
, A
0
=
000
) in waveform (a). When branched, regard-
less of the 8-byte boundary of the branch destination address,
access starting from the 4-byte boundary (the low-order 2 bits of ad-
dress, A
1
, A
0
=
00
) is performed in waveform (b). Once the 8-byte
boundary has been selected, instructions will be prefetched in wave-
form (a) until a branch.
相關PDF資料
PDF描述
M37920FCCGP Single Chip 16 Bits CMOS Microcomputer(16位單片機)
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M3802 Single Chip 8 Bits Microcomputer(8位單片機)
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