
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
104
Fig. 103 Bit configuration of particular function select register 1
7
6
5
4
3
2
1
0
Particular function select register 1
STP-instruction-execution status bit
(Note 1)
0: Normal operation.
1: STP instruction has been executed.
WIT-instruction-execution status bit
(Note 1)
0: Normal operation.
1: WIT instruction has been executed.
Standby state select bit
0: External bus
1: Programmable I/O port
Internal clock stop select bit at WIT
(Note 2)
0: In wait mode, internal peripheral devices
’
operation clock is active.
1: In wait mode, internal peripheral devices
’
operation clock is stopped.
“
0
”
at read.
Address
63
16
Notes 1:
At power-on reset, this bit becomes
“
0
”
. At hardware reset or software reset, this bit retains
the status just before reset. Even when
“
1
”
is written, the bit status will not change.
2:
Setting this bit to
“
1
”
must be performed just before execution of the WIT instruction.
Also, after the WIT state is terminated, this bit must be cleared to
“
0
”
immediately.
Fig. 102 Bit configuration of particular function select register 0
7
6
5
4
3
2
1
0
Particular function select register 0
External clock input select bit
(Note)
0: Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1: Oscillation circuit is inactive. (Clock which is generated in the external is input.)
Watchdog timer is not used at stop mode termination.
“
0
”
at read.
STP instruction invalidity select bit
0: STP instruction is valid.
1: STP instruction is invalid.
Address
62
16
Note:
Writing to these bits requires the following procedure:
Write
“
55
16
”
to this register. (The bit status does not change only by this writing.)
Succeedingly, write
“
0
”
or
“
1
”
to each bit.
troller is operating, DRAM reflesh is performed. Note that the watch-
dog timer is stopped.
On the other hand, when the WIT instruction is executed with the in-
ternal clock stop select bit at WIT =
“
1
”
, the oscillation circuit is oper-
ating, while
φ
BIU
,
φ
CPU
, and divide clocks f
1(
φ
)
to f
4096
stop operating.
As a result, the A-D converter, DMA controller, and watchdog timer,
which use divide clocks f
1(
φ
)
to f
4096
, Wf
32
and Wf
512
, are stopped.
Because the reflesh timer of the DRAM controller is operating,
DRAM reflesh is performed. At this time, timers A and B operate only
in the event counter mode, and serial I/O communication is active
only while an external clock is selected. If the internal peripheral de-
vices are not used in the WIT mode, the latter is better because the
current dissipation is more saved. Note that the internal clock stop
select bit at WIT is to be set to
“
1
”
immediately before execution of
the WIT instruction and cleared to
“
0
”
immediately after the WIT
mode is terminated.
The WIT state is terminated by acceptance of an interrupt request,
and then, supply of
φ
BIU
and
φ
CPU
will restart. Since the oscillation
circuit is operating in the WIT mode, an interrupt processing can be
executed just after the WIT mode termination.