
33
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
7
6
5
4
3
2
1
0
CS
0
control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width
RDY control bit
(Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS
0
wait number select bits
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait
(Note 1)
Address
80
16
Burst ROM access select bit
(Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS
0
.
1 : Recovery cycle is inserted at access to area CS
0
.
CS
0
output select bit
0 : CS
0
output is disabled. (P9
0
functions as a programmble I/O port pin.)
1 : CS
0
output is enabled. (P9
0
functions as pin CS
0
.)
Notes 1:
When the burst ROM access is specified (bit 5= 1), be sure not to select
“
11
2
”
(ALE expansion wait).
2:
This bit is valid when the RDY input select bit (bit 2 at address 5F
16
) =
“
1
”
.
3:
While V
CC
level voltage is applied to pin BYTE, the normal access is selected regardless of this bit
’
s contents.
7
6
5
4
3
2
1
0
CS
1
control register L
CS
2
control register L
CS
3
control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width
(Note 2)
RDY control bit
(Note 3)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS
j
wait number select bits (j = 1 to 3)
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait
(Note 1)
DRAM space select bit
0 : Except DRAM space
1 : DRAM space
Address
82
16
84
16
86
16
Burst ROM access select bit
(Note 4)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
(Note 5)
0 : No recovery cycle is inserted at access to area CS
j
.
1 : Recovery cycle is inserted at access to area CS
j
.
CS
j
output select bit (j = 1 to 3)
0 : CS
j
output is disabled. (P9
j
functions as programmable I/O port pins.)
1 : CS
j
output is enabled. (P9
j
functions as pin CS
j
.)
Notes 1:
When the DRAM space is specified (bit 4 = 1), fix these bits to
“
01
2
”
(1 wait). Also, when the burst ROM access is
specified (bit 5 = 1), be sure not to select
“
11
2
”
(ALE expansion wait).
2:
While V
CC
level voltage is applied to pin BYTE, this bit is fixed to
“
1
”
(8-bit width).
3:
This bit is valid when the RDY input select bit (bit 2 at address 5F
16
) =
“
1
”
. Also, when DRAM space is specified
(bit 4 = 1), the RDY control is invalid regardless of this bit
’
s contets.
4:
When only the external data bus width select bit (bit 2) =
“
1
”
or while V
CC
level voltage is applied to pin BYTE, the
normal access is selected regardless of this bit
’
s contents.
5:
When the DRAM space is specified (bit 4 = 1), fix this bit to
“
0
”
(no recovery cycle).
“
0
”
at read.
Fig. 15 Bit configuration of CS
0
/CS
1
/CS
2
/CS
3
control register Ls