參數(shù)資料
型號： M37920FGCGP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述： 單片微機16位的CMOS（16位單片機）
文件頁數(shù)： 103/158頁
文件大?。?/td> 1261K
代理商： M37920FGCGP
103
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Stop and Wait mode
The stop (hereafter called STP) and the wait (hereafter called WIT)
modes are used to save the power dissipation of the system, by
stopping oscillation or system clock in the case that the CPU needs
not be operating.
The microcomputer enters the STP or WIT mode by executing the
STP or WIT instruction, and either mode is terminated by acceptance
of an interrupt request or reset.
To terminate the STP or WIT mode by an interrupt request, the inter-
rupt to be used for termination of the STP or WIT mode must be en-
abled in advance to execution of the STP or WIT instruction. The
interrupt priority level of this interrupt is required to be higher than the
processor interrupt priority level (IPL) of the routine where the STP
or WIT instruction will be executed.
Figures 102 and 103 show the bit configurations of the particular
function select registers 0, 1. Setting the STP instruction invalidity
select bit (bit 0 of the particular function select register 0) to
“
1
”
invali-
dates the STP instruction, and the STP instruction will be ignored.
After reset is removed, since the above bit is cleared to
“
0
”
, however,
the STP instruction is valid.
The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the
particular function select register 1) is set to
“
1
”
by the execution of
the STP or the WIT instruction, and so, after the STP or WIT mode
has been terminated, each bit will indicate that the STP or WIT in-
struction has been executed. Accordingly, each of these bits must be
cleared to
“
0
”
by software at termination of the STP or the WIT mode.
Table 23 lists the microcomputer
’
s operation in the STP and WIT
modes.
STP mode
The execution of the STP instruction stops the oscillation circuit. It
also stops clock source
φ
,
φ
1
,
φ
BIU
,
φ
CPU
, and divide clocks f
1(
φ
)
to
f
4096
, Wf
32
and Wf
512
in the
“
L
”
state. In the watchdog timer,
“
FFF
16
”
is automatically set, and regardless the contents of watchdog timer
frequency select bit (bit 0 at address 61
16
), the count source of the
watchdog timer becomes Wf
32
. This setting is terminated by clear-
ance of the most significant bit of the watchdog timer or reset, and
the count source is back to the one which was selected with the
watchdog timer frequency select bit.
In the STP mode, the A-D converter, DMA controller, DRAM control-
ler (Reflesh timer is also stopped.), and watchdog timer, which use
divide clocks f
1(
φ
)
to f
4096
, Wf
32
and Wf
512
, are stopped. At this time,
timers A and B operate only in the event counter mode, and serial
I/O communication is active only while an external clock is selected.
The STP mode is terminated by acceptance of an interrupt request
or reset, and the oscillation restarts. Supply of clock source
φ
,
φ
1
, di-
vide clocks f
1(
φ
)
to f
4096
, Wf
32
and Wf
512
is also restarted.
When the oscillation is restarted by the interrupt request acceptance,
φ
BIU
and
φ
CPU
are stopped at
“
L
”
level until the most significant bit of
the watchdog timer, which is counted down with divide clock Wf
32
, is
cleared to
“
0
”
. Note that, when the oscillation is restarted, supply of
φ
BIU
and
φ
CPU
starts immediately after the oscillation restarts. There-
fore, the reset input must be raised to
“
H
”
after the enough oscilla-
tion-stabilizing time has elapsed.
The system where a stable clock is input from the external to pin X
IN
is equipped with the mode where an instruction can be executed
immediately after the STP mode termination. For details, refer to the
section on
“
Stop of oscillation circuit
”
of the power saving function.
WIT mode
When the WIT instruction is executed with the internal clock stop se-
lect bit at WIT (bit 3 of the particular function select register 1 in Fig-
ure 103) =
“
0
”
,
φ
BIU
,
φ
CPU
, and divide clocks Wf
32
and Wf
512
are
stopped in the
“
L
“
state. However, the oscillation circuit, clock source
φ
,
φ
1
, and divide clocks f
1(
φ
)
to f
4096
remain operating. Therefore,
BIU, CPU, and DMA controller are stopped, whereas timers A and B,
serial I/O, and the A-D converter, which use the divide clocks f
1(
φ
)
to
f
4096
, are still operating. Because the reflesh timer of the DRAM con-
Instruction
WIT
Internal clock
stop select bit
at WIT
Active
Oscillation
circuit
Operations in WIT and STP modes
“
0
”
φ
,
φ
1
,
f
1(
φ
)
to f
4096
Active
STP
Wf
32
, Wf
512
φ
BIU
,
φ
CPU
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Peripheral devices using f
1(
φ
)
to f
4096
, Wf
32
, Wf
512
Timers A, B, Serial I/O, A-D converter: Operation is enabled.
DRAM controller: Reflesh timer is operated.
DMA controller: Stopped. (Watchdog timer: Stopped.)
Timers A, B: Operation is enabled only in the event counter mode.
Serial I/O: Operation is enabled only while an external clock is
selected.
A-D converter, DMA controller: Stopped.
DRAM controller: Reflesh timer is operated.
(Watchdog timer: Stopped.)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Active
“
1
”
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
Timers A, B: Operation is enabled only in the event counter mode.
Serial I/O: Operation is enabled only while an external clock is
selected.
A-D converter, DMA controller: Stopped.
DRAM controller: Stopped. (Reflesh timer is also stopped.)
(Watchdog timer: Stopped.)
—
Table 23. Microcomputer
’
s operation in STP and WIT modes
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