參數(shù)資料
型號(hào)： M37920FGCGP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 70/158頁
文件大小： 1261K
代理商： M37920FGCGP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
70
DMA CONTROLLER
The DMA (direct memory access) controller is a 4-channel controller
which provides high-speed data transfers from memory to memory,
memory to input/output ports of external devices (herein referred to
as external I/O), and external I/O to memory without using the CPU.
Figure 65 shows the block diagram of the DMA controller, Figure 66
shows the DMA control-related register memory map, and Figure 67
shows the bit configuration of the DMAC control registers L and H.
DMA transfers are performed by the DMA control circuit via the bus
interface unit (BIU).
Each of DMAC control registers L and H consists of 8 bits. For
DMAC control register L, bit 0 is the priority select bit, and bit 1 is the
TC pin validity bit. Bits 4 to 7 are DMAi request bits (i = 0 to 3). Read-
ing these bits indicates whether a DMA request for each channel has
occurred or not. For DMAC control register H, bits 0 to 3 are software
DMA request bits, and each of them is used to generate a DMA re-
quest by software. Bits 4 to 7 are DMA
i
enable bits (i = 0 to 3). The
DMA request is accepted only when the corresponding DMAi enable
bit is set to
“
1
”
. All of these DMA
i
enable bits are cleared to
“
0
”
after
reset removal.
Figure 68 shows the bit configuration of the DMA
i
control register (i =
0 to 3). Each channel of the DMA
i
control register consists of 8 bits.
Bits 0 to 3 are DMA request source select bits.
Bit 4 determines whether the edge or level sense function is to be
used for selecting a request source from pin DMAREQ
i
(DMA re-
quest input). Bit 5 is the DMAACK
i
validity bit. When bit 5 is
“
0
”
, pin
DMAACK
i
(the DMA acknowledge signal output pin) is invalid; when
“
1
”
, pin DMAACK
i
is valid.
Figure 69 shows the bit configuration of the DMA
i
mode registers L
and H. Each channel of both registers consists of 8 bits. Refer to the
corresponding section for more details.
Pin description
Pins DMAREQ
i
, DMAACK
i
, TC are used for DMA transfers.
Pin DMAREQ
i
is a DMA request input pin. Port pins P6
1
, P6
3
, P6
5
,
and P6
6
are multiplexed with pins DMAREQ
0
, DMAREQ
1
,
DMAREQ
2
and DMAREQ
3
, respectively. These pins are used in or-
der to request a DMA transfer from the external.
When the DMA request source select bits (bits 0 to 3) of the DMA
i
control register are set to
“
0001
”
, the input signal from this pin be-
comes the DMA request signal. In order to use any of the above pin
as pin DMAREQ
i
, be sure to set the corresponding bit of the port P6
direction register to the input mode.
Pin DMAACK
i
is the DMA acknowledge signal output pin. Port pins
P6
0
, P6
2
, P6
4
are multiplexed with pins DMAACK
0
, DMAACK
1
, and
DMAACK
2
, respectively. When bit 5 (DMAACK
i
validity bit) of the
DMA
i
control register for each channel is set to
“
1
”
, pin DMAACK
i
serves as the output-only pin for signal DMAACK
i
. (DMA3 is not
equipped with pin DMAACK
i
.) During DMA transfer, the operating
channel acknowledge signal is output regardless of the data transfer
method (the 1-bus cycle transfer or 2-bus cycle transfer). When the
acknowledge signal is not needed, clear the DMAACK
i
validity bit to
“
0
”
, so that pin DMAACK
i
can serve as an I/O pin.
Pin TC is a terminal count pin and is multiplexed with port pin P4
2
.
Pin TC is valid when
“
1
”
has been written to bit 1 of the DMAC con-
trol register L. At this time, pin TC serves as the N-channel open
drain output pin. When the value of the transfer counter register or
transfer block counter is
“
0
”
, pin TC outputs
“
L
”
level for 1 cycle of
φ
1
.
Furthermore, when the TC pin validity bit is
“
1
”
, any ongoing channel
DMA transfer can be cancelled by changing the input level at pin TC
from
“
H
”
to
“
L
”
.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37920FGCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920S4CGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER
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