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參數(shù)資料
| 型號： | M37902FCCHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 85/143頁 |
| 文件大?。?/td> | 1148K |
| 代理商： | M37902FCCHP |
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M37902FCCHP, M37902FGCHP, M37902FJCHP
46
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 8 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as a type of interrupt in this
section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, NMI, and
address matching detection all have interrupt control registers. Table
9 shows the addresses of the interrupt control registers and Figure
35 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than watchdog timer and NMI can be cleared by software.
An NMI interrupt request is a non-maskable interrupt by an external
input and is accepted at the falling edge of an input to pin NMI. Also,
pin NMI has the pullup function. For more details, refer to the section
on input/output pins.
An INTi (i = 0 to 4) interrupt request is generated by an external in-
put.
INT0 to INT2 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
For INT3 and INT4, the interrupt signal’s polarity can be change by
the polarity select bit. (This is valid only in the edge sense.)
By pins INT2 to INT4 select bits (bits 4 to 6 at address 9416; see Fig-
ure 40.), pin position of INT2 to INT4 can be changed.
When using the following pins as external interrupt input pins, clear
the direction registers of the corresponding multiplexed ports to “0”:
pins P62/INT0, P63/INT1, P64(P77)/INT2, P80(P74)/INT3, and
P84(P75)/INT4.
Furthermore, the INT3 interrupt can function as the key input inter-
rupt. For details, refer to the section on the key input interrupt.
When the external interrupt input read register (address 9516) is read
out, the status of pins INT0 to INT4 and NMI can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be ad-
justed by software as shown in Figure 36.
The hardware priority is fixed as the following:
reset > NMI > watchdog timer > other interrupts
Interrupts
Address matching detection interrupt
INT4 external interrupt
INT3 external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2 external interrupt
INT1 external interrupt
INT0 external interrupt
NMI external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 8. Interrupt sources and interrupt vector addresses
Vector addresses
00FFCA16
00FFCB16
00FFD016
00FFD116
00FFD216
00FFD316
00FFD416
00FFD516
00FFD616
00FFD716
00FFD816
00FFD916
00FFDA16
00FFDB16
00FFDC16
00FFDD16
00FFDE16
00FFDF16
00FFE016
00FFE116
00FFE216
00FFE316
00FFE416
00FFE516
00FFE616
00FFE716
00FFE816
00FFE916
00FFEA16
00FFEB16
00FFEC16
00FFED16
00FFEE16
00FFEF16
00FFF016
00FFF116
00FFF216
00FFF316
00FFF416
00FFF516
00FFF616
00FFF716
00FFF816
00FFF916
00FFFA16
00FFFB16
00FFFC16
00FFFD16
00FFFE16
00FFFF16
Fig. 34 Bit configuration of external interrupt input read register
76543210
Note: When the key input interrupt select bit (bit 0 at address 9416) = “1”,
the status of pin INT3 cannot be read out.
INT0 read bit
INT1 read bit
INT2 read bit
INT3 read bit (Note)
INT4 read bit
NMI read bit
Undefined at read.
External interrupt input read register
Address
9516
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