- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98007 > M37902FCCHP 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | M37902FCCHP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 72/143頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | M37902FCCHP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)當(dāng)前第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
34
Notes 1: For details of the processor mode setting, see Table 3.
2: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16).
3: The middle-order/high-order address output pins in the memory expansion or microprocessor mode can be switched to I/O port pins by the address/port
switch select bits of the port function control register (bits 2 to 0 at address 9216).
4: When the external data bus width for the chip select area, CS2, has been set to 8 bits, only in the access to area CS2, by the multiplexed bus select bit
of the CS2 control register H (bit 5 at address 8516), a multiplexed bus which performs the following operations with the time-sharing method is realized:
Output of address LA0 to LA7
Input/Output of data D0 to D7
5: When one of areas CS1/CS2/CS3 is accessed under the following conditions, pins D8 to D15 enter the floating state, and pin BHW outputs “H” level.
(They do not become I/O port pins.)
Pin BYTE is at Vss level.
One of bit 2s at addresses 8216, 8416, 8616 (the external data bus width select bit of the CS1/CS2/CS3 control register L) is set to “1” (external data bus
width = 8 bits).
6: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E16, 5F16), port pins P30, P40 to
P43 can operate as pins for RDY input, ALE output,
φ1 output, HLDA output, HOLD input, respectively.
In the microprocessor mode, by the above select bits, the above pins (RDY, ALE,
φ1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respec-
tively.
In the single-chip mode, port pin P41 can operate as the
φ1 output pin by the above select bits.
7: In the memory expansion mode, port pin P44 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address
8016).
8: In the memory expansion and microprocessor modes, port pins P45 to P47 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i =
1 to 3) (bit 7s at addresses 8216, 8416, 8616).
Table 6. Relationship between processor modes, memory area, and port function (2)
Single-chip mode
I/O port pin P40
I/O port pin P41
Clock
φ1 is output (Note 6).
I/O port pin P42
I/O port pin P43
I/O port pin P44
I/O port pins P45 to P47
Port pin P40
Port pin P41
Port pin P42
Port pin P43
Port pin P44
Port pins P45 to P47
Memory expansion mode
I/O port pin P40
Address latch enable signal
ALE is output (Note 6).
I/O port pin P41
Clock
φ1 is output (Note 6).
I/O port pin P42
Hold acknowledge signal
HLDA is output (Note 6).
I/O port pin P43
Hold request signal
HOLD is input (Note 6).
I/O port pin P44
Chip select signal CS0 is output
(Note 7).
I/O port pins P45 to P47
Chip select signals CS1 to CS3 are
output (Note 8).
Microprocessor mode
Address latch enable signal
ALE is output.
I/O port pin P40 (Note 6)
Clock
φ1 is output.
I/O port pin P41 (Note 6)
Hold acknowledge signal
HLDA is output.
I/O port pin P42 (Note 6)
Hold request signal
Signal HOLD is input.
I/O port pin P43 (Note 6)
Chip select signal CS0 is output.
I/O port pin P45 to P47
Chip select signals CS1 to CS3 are
output (Note 8).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37902FGCHP | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| M37906F8CSP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP42 |
| M37906F8CFP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO42 |
| M37906F8CSP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP42 |
| M37920S4CGP | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37902FGCGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FGCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FJCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37903S4CHP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
| M37905F8CFP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。