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參數(shù)資料
| 型號： | M37902FCCHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 70/143頁 |
| 文件大小： | 1148K |
| 代理商： | M37902FCCHP |
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
32
Signal
RD
BLW
BHW
ALE
φ1
RDY
HOLD
HDLA
CS0–CS3
BYTE
VSS
VCC
00
01
10
MD0
Processor mode bits
After reset is removed, the single-chip mode is selected. By chang-
ing the processor mode bits’ contents by software, the memory ex-
pansion mode or microprocessor mode can be selected.
Description
(Note 1)
Processor mode
After reset is removed, the microprocessor mode is selected.
(Note 2)
Single-chip mode
Memory expansion mode
Microprocessor mode
Table 3. Selection method of processor mode
Table 4. Each bus control signal’s function
I/O
Output
Input
Output
Input
Function
Read signal. Outputs “L” at read from the external area.
Write signal. Outputs “L” at write to the external area.
Address latch enable signal. Outputs “H” level pulse in the
period just before signals RD, BLW, BHW become “L”.
This is used to latch an address in an external circuit.
Internal standard clock’s output. Outputs system clock
(fsys).
Ready signal. The “L” level period of the last
φ1 in the ac-
cess cycle for the external area (in other words, “L” level
period of RD, BLW, BHW) will be extended while “L” level
voltage is applied to this pin.
Hold request signal. Appliance of “L” level voltage will gen-
erate a hold request; appliance of “H” level voltage will re-
quest to terminate the hold state.
Hold acknowledge signal. Outputs “L” in the hold state.
Chip select signal. Outputs “L” in access to the specified
chip select area.
Input signal to select the external data bus width. When
this pin’s level = Vss, 16-bit width will be selected; and
when Vcc, 8-bit width will be selected.
Remarks
For operation differences between BLW and BHW de-
pending on the external data bus width, see Table 5.
In order to latch an address with signal ALE, do as follows:
While ALE = “H”, be sure to open a latch, so the address
will pass it.
While ALE = “L”, be sure to hold the address.
Acceptance and termination of a hold request is performed
at completion of the bus cycle while the BIU operates.
In the hold state, A0–A23, D0–D15, RD, BLW, BHW, ALE,
CS0–CS3 enter the floating state. At termination of the hold
state, simultaneously with the timing when HLDA becomes
“H” level, the above floating state is terminated. Then, bus
access will be restarted 1 cycle of
φ1 after.
In the hold state, also, the CPU operates with access to
the internal area. If the CPU accesses the external area, in
the hold state, the CPU stops its operation.
For details, refer to the section on the chip select wait con-
troller.
When BYTE = Vss level, by the register setting, each chip
select area (CS1 to CS3) can have the 8-bit data bus, inde-
pendently.
For details, refer to the section on the chip select wait con-
troller.
Notes 1: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16)
2: While the Vcc level voltage is applied to pin MD0, the processor mode bits are fixed to “10”.
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