
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
76
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter.
Figure 77 shows the block diagram of the A-D converter, Figure 78
shows the bit configuration of the A-D control register 0 (address
1E16), and Figure 79 shows the bit configuration of the A-D control
register 1 (address 1F16).
A-D conversion accuracy
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even address of the cor-
responding A-D register and the high-order 2 bits are stored in bits 0
and 1 at the odd address of the corresponding A-D register. Bits 2 to
7 of the A-D register odd address are “0000002” when read.
Fig. 77 Block diagram of A-D converter
When the conversion result is used as 8-bit data, the conversion re-
sult are stored in even address of the corresponding A-D register. In
this case, the value at the A-D register’s odd address is “0016” when
read.
A-D conversion frequency
An operation clock (
φAD) of an A-D converter can be selected with bit
7 of the A-D control register 0 and bit 4 of the A-D control register 1.
When bit 4 of the A-D control register 1 is “0”,
φAD becomes f2/4
when bit 7 of the A-D control register 0 is “0”,
φAD becomes f2/2 when
bit 7 of the A-D control register 0 is “1”.
When bit 4 of the A-D control register 1 is “1”,
φAD becomes f2 when
bit 7 of the A-D control register 0 is “0”,
φAD becomes f1 when bit 7 of
the A-D control register 0 is “1”. Note that
φAD = f1 (in other words,
the fastest speed) can be selected only in the 8-bit mode.
φAD during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Comparator
Resistor ladder network
Selector
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7/ADTRG
Vref
Successive
approximation register
A-D register 0
A-D register 1
A-D register 2
A-D register 3
Data bus (odd)
A-D control register 1
A-D control register 0
φAD
A-D conversion frequency
(
φAD) select bit 1,0
(1,1)
A-D conversion
frequency selection
f2
(1,0)
(0,1)
(0,0)
1/2
f1
Data bus (even)
AVSS
VREF
0
1
VREF connection select bit
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Decoder