參數(shù)資料
型號： M37902FCCHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 140/143頁
文件大?。?/td> 1148K
代理商： M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
96
Fig. 101 Bit configuration of particular function select register 1
Fig. 102 Bit configuration of watchdog timer frequency select register
7
6
543
2
1
0
Particular function select register 1
STP-instruction-execution status bit (Note 1)
0: Normal operation.
1: STP instruction has been executed.
WIT-instruction-execution status bit (Note 1)
0: Normal operation.
1: WIT instruction has been executed.
Standby state select bit
0: External bus
1: Programmable I/O port
System clock stop select bit at WIT (Note 2)
0: In wait mode, system clock fsys is active.
1: In wait mode, system clock fsys is stopped.
Address output select bit
0: Address changes depending on bus access.
1: Address changes only at access to external address.
Timer B2 clock source select bit
In event counter mode:
0: Clock input from pin TB2IN is counted.
1: fX32 (f(XIN)/32) is counted.
Address
6316
Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit
retains the value just before reset. Even when “1” is written, the bit status will not change.
2: Setting this bit to “1” must be performed just before execution of the WIT instruction.
Also, after the wait state is terminated, this bit must be cleared to “0” immediately.
76543210
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Select W f512
1 : Select W f32
Watchdog timer clock source select bits at STP termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
76543210
Address
6116
down with one of the above divide clocks, fX16 to fX128, after the os-
cillation circuit and PLL circuit have been restarted their operations
owing to an interrupt. The most significant bit of the watchdog timer
reaching “0”, supply of
φBIU and φCPU restarts.
On the other hand, when the external clock input select bit = “1 ” and
the system clock select bit = “0”, supply of
φBIU and φCPU will restart
immediately after the oscillation circuit has been restarted their op-
erations owing to an interrupt. (In actual fact, after the selected one
of the above divide clocks, fX16 to fX128, has been changed from “H”
to “L”, this supply will restart.)
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