參數(shù)資料
型號： M37902FCCHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 71/143頁
文件大?。?/td> 1148K
代理商： M37902FCCHP
33
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Microprocessor mode
VCC level voltage is applied
10
SFR area
Internal RAM area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is
output.
I/O port pins P110 to P117
(Note 3)
High-order address (A16 to A23) is out-
put.
I/O port pins P00 to P07
(Note 3)
Low-order data (D0 to D7, data at
even address) is input/output.
Low-order data (D0 to D7, data at
even/odd address) is input/output.
Low-order address (LA0 to LA7) is out-
put. Low-order data (D0 to D7, data at
even/odd address) is input/output
(Note 4).
High-order data (D8 to D15, data at
odd address) is input/output.
I/O port pins P20 to P27 (Note 5)
Ready signal RDY is input.
I/O port pin P30 (Note 6)
Read signal RD is output
Write signal BLW (write to even ad-
dress) is output.
Write signal BLW (write to even/odd
address) is output.
Write signal BHW (write to odd ad-
dress) is output.
I/O port pin P33 (Note 5)
Memory expansion mode
VSS level voltage is applied
01
SFR area
Internal RAM area
Internal ROM area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is
output.
I/O port pins P110 to P117
(Note 3)
High-order address (A16 to A23) is out-
put.
I/O port pins P00 to P07
(Note 3)
Low-order data (D0 to D7, data at
even address) is input/output.
Low-order data (D0 to D7, data at
even/odd address) is input/output.
Low-order address (LA0 to LA7) is out-
put. Low-order data (D0 to D7, data at
even/odd address) is input/output
(Note 4).
High-order data (D8 to D15, data at
odd address) is input/output.
I/O port pins P20 to P27 (Note 5)
I/O port pin P30
Ready signal RDY is input (Note 6).
Read signal RD is output.
Write signal BLW (write to even ad-
dress) is output.
Write signal BLW (write to even/odd
address) is output.
Write signal BHW (write to odd ad-
dress) is output.
I/O port pin P33 (Note 5)
Table 5. Relationship between processor modes, memory area, and port function (1)
Mode
(Note 1)
Single-chip mode
VSS level voltage is applied
00
SFR area
Internal RAM area
Internal ROM area
(Do not access.)
I/O port pins P100 to P107
I/O port pins P110 to P117
I/O port pins P00 to P07
I/O port pins P10 to P17
I/O port pins P20 to P27
I/O port pin P30
I/O port pin P31
I/O port pin P32
I/O port pin P33
Memory
area
Port pins P100 to P107
Port pins P110 to P117
Port pins P00 to P07
Port pins
P10 to P17
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 8 bits
Port pins
P20 to P27
Port pin P30
Port pin P31
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
Port pin
P32
Port pin
P33
External data bus
width = 8 bits
Pin MD0
Processor mode
bits (Note 2)
SFR area
Internal RAM area
Internal ROM area
Other area
External data bus
width = 16 bits
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