參數(shù)資料
型號(hào): M37902FCCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 114/143頁(yè)
文件大?。?/td> 1148K
代理商: M37902FCCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
72
Fig. 73 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
Fig. 74 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
ASYNCHRONOUS
SERIAL COMMUNICATION
Asynchronous serial communication can be performed using 7-, 8-, or
9-bit length data. The operation is the same for all data lengths. The
following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, bit 0 of UARTi transmit/re-
ceive mode register is “1”, bit 1 is “0”, and bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, bit 0 (CS0) and bit 1 (CS1)
of UARTi transmit/receive control register 0 are used to select the
clock source. When an internal clock is selected for asynchronous
serial communication, the CLKi pin can be used as a normal I/O pin.
The selected internal or external clock is divided by (n+1), then by
16, and is passed through a control circuit to create the UART trans-
mission clock or UART receive clock.
Therefore, the transmission speed can be changed by changing the
contents (n) of the bit rate generator. If the selected clock is an inter-
nal clock Pfi or an external clock fEXT,
Bit Rate = (fi or fEXT) / {(n+1)
×16}
Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
Bit 5 is a select bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of 1s
in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1s in the data and parity bit is always even.
Bit 6 is the parity bit select bit which indicates whether to add parity
bit or not.
Bits 4 to 6 must be set or reset according to the data format used in
the communicating devices.
Bit 7 is the sleep select bit. The sleep mode is described later.
Figure 76 shows the bit configuration of the serial I/O pin control reg-
________ ________
ister. By bits 0 and 1 of the serial I/O pin control register (CTSi/RTSi
_______ _______
separate select bits), the function of the CTS/RTS pin can be sepa-
rated into two functions, and each function can be assigned to two
different pins. When bits 0 and 1 = “11”, the above separation is per-
formed. When bits 0 and 1 = “00”, no separation is performed.
_______ _______
Table 13 lists the selection methods of the CTS/RTS function.
(1/fi or 1/fEXT)
× (n + 1) × 16
Written in transmit buffer register
Transmission clock
TEi
TIi
CTSi
TENDi
TXDi
TXEPTYi
D0 D1
ST
Start bit
Parity bit Stop bit
D2 D3 D4 D5 D6 D7
PSP ST D0 D1 D2 D3 D4 D5 D6 D7
PSP
ST D0 D1
Transmit register
← Transmit
buffer register
Stopped because TEi = “0”
(1/fi or 1/fEXT)
× (n + 1) × 16
Written in transmit buffer register
Transmission clock
TEi
TIi
TENDi
TXDi
TXEPTYi
D0 D1
ST
D2 D3 D4 D5 D6 D7 D8
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0
D2
D1
Transmit register
← Transmit
buffer register
Stopped because TEi = “0”
Start bit
Stop bit
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