- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45026 > M32180F8VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240 PDF資料下載
參數(shù)資料
| 型號(hào)： | M32180F8VFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240 |
| 封裝： | 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件頁(yè)數(shù)： | 56/139頁(yè) |
| 文件大?。?/td> | 3774K |
| 代理商： | M32180F8VFP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
1-6
1
OVERVIEW
32180 Group User’s Manual (Rev.1.0)
1.2 Block Diagram
Table 1.2.1 Features of the 32180 (1/2)
Functional Block
Features
M32R-FPU CPU core
Implementation: Five-stage pipelined instruction processing (processed in six stages when
performing floating-point arithmetic)
Internal 32-bit structure of the core
Register configuration
General-purpose registers: 32 bits × 16 registers
Control registers: 32 bits × 6 registers
Instruction set
16 and 32-bit instruction formats
100 discrete instructions and six addressing modes
Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)
Internal single-precision floating-point arithmetic unit (FPU)
RAM
Capacity: 48 Kbytes, accessible with zero wait state
The internal RAM can be accessed for reading or rewriting data from the outside independently of
the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to
decrease.
Flash memory
Capacity: 1 Mbytes (1,024 Kbytes), accessible with one wait state
Durability: Rewritable 100 times
Bus specification
Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)
Logical address space : 4 Gbytes linear
Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)
(or accessed in 64 bits when accessing the internal flash memory for
instructions)
: Internal 16-bit data bus (for internal peripheral I/O access)
External area: Maximum 8 Mbytes (during processor mode)
Extended external area: Maximum 8 Mbytes (1 Mbytes + 2 Mbytes × 3 blocks during external
extension mode)
External data address: 20-bit address
External data bus: 16-bit data bus
Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write
Multijunction timer (MJT)
64-channel multi-functional timer
16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,
16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels,
16-bit input related up/down timer × 3 channels, and 24-bit output related timer × 24 channels
Flexible timer configuration is possible by interconnecting these timer channels.
Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level
from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)
DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or
low level from the TIN pin (These can be used as external DMA transfer request inputs
irrespective of timer
operation.)
DMAC
Number of channels: 10
Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O
and internal RAM are supported.
Capable of advanced DMA transfers when used in combination with internal peripheral I/O
Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)
DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a
transfer on another channel.)
Interrupt request: DMA transfer counter register underflow
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M32182F3VFP | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3UFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3VFP | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M32180T2-PTC | 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁(yè)面:1429 (CN2011-ZH PDF) |
| M32182F3TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3UFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3VFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。
