參數(shù)資料
型號(hào): M32180F8VFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝: 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁(yè)數(shù): 24/139頁(yè)
文件大小: 3774K
代理商: M32180F8VFP
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12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-32
12.4.1
Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-32
12.4.2
Starting CSIO Reception ------------------------------------------------------------------------------------- 12-34
12.4.3
Processing at End of CSIO Reception -------------------------------------------------------------------- 12-34
12.4.4
About Successive Reception -------------------------------------------------------------------------------- 12-35
12.4.5
Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-36
12.4.6
Example of CSIO Receive Operation --------------------------------------------------------------------- 12-37
12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-39
12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-40
12.6.1
Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-40
12.6.2
UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-40
12.6.3
Initializing UART Transmission ----------------------------------------------------------------------------- 12-42
12.6.4
Starting UART Transmission -------------------------------------------------------------------------------- 12-44
12.6.5
Successive UART Transmission --------------------------------------------------------------------------- 12-44
12.6.6
Processing at End of UART Transmission --------------------------------------------------------------- 12-44
12.6.7
Transmit Interrupts --------------------------------------------------------------------------------------------- 12-44
12.6.8
Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-45
12.6.9
Example of UART Transmit Operation -------------------------------------------------------------------- 12-46
12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-48
12.7.1
Initialization for UART Reception --------------------------------------------------------------------------- 12-48
12.7.2
Starting UART Reception ------------------------------------------------------------------------------------ 12-50
12.7.3
Processing at End of UART Reception ------------------------------------------------------------------- 12-50
12.7.4
Example of UART Receive Operation -------------------------------------------------------------------- 12-52
12.7.5
Start Bit Detection during UART Reception -------------------------------------------------------------- 12-54
12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-55
12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-56
CHAPTER 13 CAN MODULE
13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2
13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4
13.2.1
CAN Control Registers ---------------------------------------------------------------------------------------- 13-15
13.2.2
CAN Status Registers ----------------------------------------------------------------------------------------- 13-18
13.2.3
CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21
13.2.4
CAN Configuration Registers -------------------------------------------------------------------------------- 13-22
13.2.5
CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24
13.2.6
CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25
13.2.7
CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26
13.2.8
CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27
13.2.9
CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45
13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46
13.2.11 CAN DMA Transfer Request Select Registers ---------------------------------------------------------- 13-47
13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48
13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52
13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53
13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57
13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72
13.3.1
CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72
13.3.2
Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73
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