參數(shù)資料
型號： M32180F8VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝： 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁數(shù)： 109/139頁
文件大小： 3774K
代理商： M32180F8VFP
3
3-20
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
32180 Group User’s Manual (Rev.1.0)
SFR Area Register Map (13/27)
Address
+0 address
+1 address
See pages
b0
b7 b8
b15
H'0080 07C4
TOU0_6 Reload Register
TOU0_6 Reload 1 Register
10-164
(TOU06RLW)
(TOU06RL1)
10-167
H'0080 07C6
TOU0_6 Reload 0 Register
10-166
(TOU06RL0)
H'0080 07C8
TOU0_7 Counter
(Upper)
10-161
(TOU07CTW)
(TOU07CTH)
H'0080 07CA
(Lower)
10-163
(TOU07CT)
H'0080 07CC
TOU0_7 Reload Register
TOU0_7 Reload 1 Register
10-164
(TOU07RLW)
(TOU07RL1)
10-167
H'0080 07CE
TOU0_7 Reload 0 Register
10-166
(TOU07RL0)
H'0080 07D0
Prescaler Register 3
TID0 Control & Prescaler 3 Enable Register
10-12
(PRS3)
(TID0PRS3EN)
10-141
H'0080 07D2
TOU0 Interrupt Request Mask Register
TOU0 Interrupt Request Status Register
10-58
(TOU0IMA)
(TOU0IST)
H'0080 07D4
(Use inhibited area)
F/F21–28 Protect Register
10-31
(FF2128P)
H'0080 07D6
(Use inhibited area)
F/F21–28 Data Register
10-33
(FF2128D)
H'0080 07D8
TOU0 Control Register 1
10-158
(TOU0CR1)
H'0080 07DA
TOU0 Control Register 0
10-158
(TOU0CR0)
H'0080 07DC
(Use inhibited area)
TOU0 Enable Protect Register
10-168
(TOU0PRO)
H'0080 07DE
(Use inhibited area)
TOU0 Count Enable Register
10-169
(TOU0CEN)
H'0080 07E0
PWMOFF0 Input Processing Control Register
TIN24, 25 Input Processing Control Register
10-171
(PWMOFF0CR)
(TIN2425CR)
10-25
H'0080 07E2
TIN24, 25 Interrupt Request Mask Register
TIN24, 25 Interrupt Request Status Register
10-53
(TIN2425IMA)
(TIN2425IST)
(Use inhibited area)
H'0080 0A00
SIO45 Interrupt Request Status Register
SIO45 Interrupt Request Enable Register
12-9
(SI45STAT)
(SI45EN)
12-10
H'0080 0A02
SIO45 Interrupt Source Select Register
(Use inhibited area)
12-11
(SI45SEL)
(Use inhibited area)
H'0080 0A10
SIO4 Transmit Control Register
SIO4 Transmit/Receive Mode Register
12-14
(S4TCNT)
(S4MOD)
12-15
H'0080 0A12
SIO4 Transmit Buffer Register
12-18
(S4TXB)
H'0080 0A14
SIO4 Receive Buffer Register
12-19
(S4RXB)
H'0080 0A16
SIO4 Receive Control Register
SIO4 Baud Rate Register
12-20
(S4RCNT)
(S4BAUR)
12-23
(Use inhibited area)
H'0080 0A20
SIO5 Transmit Control Register
SIO5 Transmit/Receive Mode Register
12-14
(S5TCNT)
(S5MOD)
12-15
H'0080 0A22
SIO5 Transmit Buffer Register
12-18
(S5TXB)
H'0080 0A24
SIO5 Receive Buffer Register
12-19
(S5RXB)
H'0080 0A26
SIO5 Receive Control Register
SIO5 Baud Rate Register
12-20
(S5RCNT)
(S5BAUR)
12-23
(Use inhibited area)
H'0080 0A80
A-D1 Single Mode Register 0
A-D1 Single Mode Register 1
11-16
(AD1SIM0)
(AD1SIM1)
11-18
H'0080 0A82
(Use inhibited area)
H'0080 0A84
A-D1 Scan Mode Register 0
A-D1 Scan Mode Register 1
11-20
(AD1SCM0)
(AD1SCM1)
11-22
H'0080 0A86
A-D1 Disconnection Detection Assist Function Control Register
A-D1 Conversion Speed Control Register
11-25
(AD1DDACR)
(AD1CVSCR)
11-24
H'0080 0A88
A-D1 Successive Approximation Register
11-29
(AD1SAR)
|
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