參數(shù)資料
型號(hào): M32180F8VFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝: 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁(yè)數(shù): 135/139頁(yè)
文件大?。?/td> 3774K
代理商: M32180F8VFP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)當(dāng)前第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
4
4-6
EIT
32180 Group User’s Manual (Rev.1.0)
4.2.3 Trap
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector
addresses are provided corresponding to TRAP instruction operands 0–15.
4.3 EIT Processing Procedure
EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which
they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted,
except for a rest interrupt, is shown below.
4.2 EIT Events
Figure 4.3.1 Outline of the EIT Processing Procedure
When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described
later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for
the EIT handler (not the jump address itself) is written.
In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s
PSW field is transferred to the BPSW field in that register.
Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and
PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the
stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember
that all these registers must be saved to the stack in a program by the user.
When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute
the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed
when the EIT occurred. (This does not apply to the System Break Interrupt, however.)
In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field
is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW
field after executing the RTE instruction are undefined.
Instruction
A
PC
→BPC
PSW
→BPSW
EIT vector
entry
EIT handler except for SBI
RTE
instruction
Program suspended
and EIT request
accepted
Instruction
processing-canceled
type (RIE, AE)
Instruction processing-completed
type (FPE, EI, TRAP)
Program execution restarted
EIT request
generated
Hardware preprocessing
BPC, PSW, FPSR
and general-purpose
registers are saved
to the stack
Branch
instruction
General-purpose
registers, PSW, FPSR
and BPC are restored
from the stack
Hardware postprocessing
(SBI)
Program terminated
or system is reset
User-created EIT handler
BPSW
→PSW
BPC
→PC
Processing
by handler
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
(Note 1)
SBI
(System Break
Interrupt processing)
Instruction
B
Instruction
C
Instruction
C
Instruction
D
相關(guān)PDF資料
PDF描述
M32182F3VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3UFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3TFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3TFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M32180T2-PTC 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁(yè)面:1429 (CN2011-ZH PDF)
M32182F3TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3UFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3VFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F8TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES