參數(shù)資料
型號： M32180F8VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝： 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁數(shù)： 13/139頁
文件大?。?/td> 3774K
代理商： M32180F8VFP
(6)
CHAPTER 11 A-D CONVERTERS
11.1 Outline of A-D Converters --------------------------------------------------------------------------------------------- 11-2
11.1.1
Conversion Modes --------------------------------------------------------------------------------------------- 11-6
11.1.2
Operation Modes ----------------------------------------------------------------------------------------------- 11-6
11.1.3
Special Operation Modes ------------------------------------------------------------------------------------ 11-9
11.1.4
A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-12
11.1.5
Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-12
11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-13
11.2.1
A-D Single Mode Registers 0 ------------------------------------------------------------------------------- 11-16
11.2.2
A-D Single Mode Registers 1 ------------------------------------------------------------------------------- 11-18
11.2.3
A-D Scan Mode Registers 0 --------------------------------------------------------------------------------- 11-20
11.2.4
A-D Scan Mode Registers 1 --------------------------------------------------------------------------------- 11-22
11.2.5
A-D Conversion Speed Control Registers --------------------------------------------------------------- 11-24
11.2.6
A-D Disconnection Detection Assist Function Control Registers ----------------------------------- 11-25
11.2.7
A-D Disconnection Detection Assist Method Select Registers ------------------------------------- 11-26
11.2.8
A-D Successive Approximation Registers --------------------------------------------------------------- 11-29
11.2.9
A-D Comparate Data Registers ----------------------------------------------------------------------------- 11-30
11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-31
11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-32
11.3 Functional Description of A-D Converters ------------------------------------------------------------------------- 11-33
11.3.1
How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-33
11.3.2
A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-34
11.3.3
Comparator Operation ---------------------------------------------------------------------------------------- 11-35
11.3.4
Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-36
11.3.5
Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-39
11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-41
11.5 Precautions on Using A-D Converters ------------------------------------------------------------------------------ 11-43
CHAPTER 12 SERIAL I/O
12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2
12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5
12.2.1
SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6
12.2.2
SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-14
12.2.3
SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-15
12.2.4
SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-18
12.2.5
SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-19
12.2.6
SIO Receive Control Registers ----------------------------------------------------------------------------- 12-20
12.2.7
SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-23
12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-24
12.3.1
Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-24
12.3.2
Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-25
12.3.3
Starting CSIO Transmission --------------------------------------------------------------------------------- 12-27
12.3.4
Successive CSIO Transmission ---------------------------------------------------------------------------- 12-27
12.3.5
Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-28
12.3.6
Transmit Interrupts --------------------------------------------------------------------------------------------- 12-28
12.3.7
Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-28
12.3.8
Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-30
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