參數(shù)資料
型號(hào)： M32180F8VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝： 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁數(shù)： 25/139頁
文件大小： 3774K
代理商： M32180F8VFP
5
5-9
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.2 ICU Related Registers
9
1011121314
b15)
(b8
123456
b7
b0
ILEVEL
IREQ
0
111
0
<After reset: H’07>
b
Bit Name
Function
R
W
0–2
No function assigned. Fix to "0"
00
(8–10)
3
IREQ
<When edge recognized>
R
W
(11)
Interrupt request bit
At read
0: Interrupt not requested
1: Interrupt requested
At write
0: Clear interrupt request
1: Generate interrupt request
<When level-recognized>
R
0
At read
0: Interrupt not requested
1: Interrupt requested
4
No function assigned. Fix to "0"
00
(12)
5–7
ILEVEL
000: Interrupt priority level 0
R
W
(13–15)
Interrupt priority level bits
001: Interrupt priority level 1
010: Interrupt priority level 2
011: Interrupt priority level 3
100: Interrupt priority level 4
101: Interrupt priority level 5
110: Interrupt priority level 6
111: Interrupt priority level 7 (interrupt disabled)
(1) IREQ (Interrupt Request) bit (Bit 3 or 11)
When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Re-
quest) bit is set to "1".
This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for
level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re-
quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not
cleared in the case of level-recognized interrupt request).
If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in
software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the
same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority.
Note: External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External
Interrupt (EI) to the CPU core can only be deasserted by the following operation:
(1) Reset
(2) IVECT register read
(3) Write to the IMASK register
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M32182F3TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3UFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3VFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F8TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
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