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| 型號(hào)： | M30240M1-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 75/125頁(yè) |
| 文件大?。?/td> | 753K |
| 代理商： | M30240M1-XXXFP |
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Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
55
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
EP0CSR5 (SETUP_END):
The USB FCU sets this bit to a “1” if a control transfer has ended before the specific length of data is trans-
ferred during the data phase. The CPU clears this bit by writing a “1” to EP0CSR7. Once the CPU sees the
SETUP_END bit set, it stops accessing the FIFO to service the previous setup transaction. If OUT_PKT_RDY
is set at the same time SETUP_END is set, it indicates the previous setup transaction ended, and a new SET-
UP token is in the FIFO.
EP0CSR6 and EP0CSR7:
These bits are used to clear EP0CSR0 and EP0CSR5 respectively. Writing a “1” to these bits clears the corre-
sponding register bit.
The USB Endpoint 0 MAXP, shown in Figure 45, indicates the maximum packet size (MAXP) of End-
point 0 IN/OUT packet. The default value for Endpoint 0 MAXP is 8 bytes. The CPU can change this
value, as negotiated with the host controller through the SET_DESCRIPTOR command.
Figure 45:
USB Endpoint 0 MAXP
The USB Endpoint 0 OUT WRT CNT register, shown in Figure 46, contains the number of bytes of
the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after
having successfully received a packet of data from the host. The CPU reads the register to determine
the number of bytes to be read from the FIFO.
Figure 46:
USB Endpoint 0 OUT WRT CNT
The USB Endpoint x IN CSR (Control & Status Register), shown in Figure 47, contains control and
status information of the respective IN endpoint 1-4.
INXCSR0 (IN_PKT_RDY) and INXCSR5 (TX_FIFO_NOT_EMPTY):
These two bits are read together to determine IN FIFO status. A “1” can be written to the INXCSR0 bit by the
CPU to indicate a packet of data is written to the FIFO (see “IN (Transmit) FIFO” operation for details).
INXCSR1 (UNDER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU
sets this bit to a “1” at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the
INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
INXCSR2 (SEND_STALL):
The CPU writes a “1” to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL
handshake while this bit is set. The CPU writes a “0” to clear this bit.
INXCSR3 (ISO):
The CPU writes a “1” to this bit to initialize the respective endpoint as an isochronous endpoint for IN trans-
actions.
INXCSR4 (INTPT):
The CPU writes a “1” to this bit to initialize this endpoint as a status change endpoint for IN transactions. This
bit is set only if the corresponding endpoint is to be used to communicate rate feedback information (see
Chapter . IN (Transmit) FIFOs for details).
EP0MXP4:0
Maximum packet size (MAXP) of Endpoint 0 IN/OUT packet.
MSB
7
LSB
0
Reserved
EP0MXP5 EP0MXP4 EP0MXP3
EP0MXP1 EP0MXP0
EP0MXP2
Access: R/W
Reset:
0816
Address: 031316
W_CNT4:0
Receive Byte Count.
MSB
7
LSB
0
Reserved Reserved Reserved
W_CNT4
W_CNT3
W_CNT1
W_CNT0
W_CNT2
Access: R
Reset:
0016
Address: 031516
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M30240M2 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M2-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M3 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M3-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M4 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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