參數(shù)資料
型號： M30240M1-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 47/125頁
文件大?。?/td> 753K
代理商： M30240M1-XXXFP
CONFIDENTIAL
30
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Interrupts
2.12 Interrupts
Table 7 and Table 8 show the interrupt sources and vector table addresses. When an interrupt is
received, the program is executed from the address shown by the respective interrupt vector.
The vector table addresses for the interrupts in Table 7 are fixed (interrupt vector addresses). These
interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupts in Table 8 are variable, being determined as relative to the
fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using
the interrupt enable flag (I flag) (maskable interrupts). 64 vectors can be set in the interrupt table register
(INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT instruction
to specify a software interrupt number, the program can be executed starting at the address indicated
by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed vector
address and variable vector address. When the contents of FFFE416 through FFFE716 are all “FF16”, the
program is executed from the address shown in the BRK instruction interrupt vector in the variable
vector address.
Specify the starting address of the interrupt program in the interrupt vector. Figure 15 shows the format
for specifying the address.
Note: Interrupts used for debugging purposes only
Figure 15:
Format for specifying interrupt vector addresses
Table 7:
Interrupt vectors (xed interrupt vector addresses)
Interrupt source
Vector table addresses
Address(L) to Address(H)
Remarks
Undened instruction
FFFDC16 to FFFDF16
Interrupt on UND instruction
Overow
FFFE016 to FFFE316
Interrupt on INTO instruction
BRK instruction
FFFE416 to FFFE716
If the vector is lled with FF16, program execution starts from
the address shown by the vector in the variable vector table
Address Match
FFFE816 to FFFEB16
There is an address-matching interrupt enable bit
Single Step (Note)
FFFEC16 to FFFEF16
Do not use
Watchdog timer
FFFF016 to FFF316
DBC (Note)
FFFF416 to FFFF716
Do not use
NMI
FFFF816 to FFFFB16
External interrupt by NMI pin
Reset
FFFFC16 to FFFFF16
Mid address
Low address
0 0 0 0
High address
0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
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