參數(shù)資料
型號(hào): M30240M1-XXXFP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù): 111/125頁(yè)
文件大?。?/td> 753K
代理商: M30240M1-XXXFP
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CONFIDENTIAL
88
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
UART0 through UART2
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 23
and Table 24 list the specifications of the clock synchronous serial I/O mode. Figure 82 shows the
UARTi transmit/receive mode register.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi
receive interrupt request bit is not set to “1”.
Table 23:
Specications of clock synchronous serial I/O mode (1)
Item
Specication
Transfer data format
Transfer data length: 8 bits
Transfer clock
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :
=2(n+1) (Note 1)
= f1, f8, f32
When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input
from CLKi pin (Note 2)
Transmission/reception
control
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start
condition
To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit buffer empty ag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_ When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start
condition
To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit buffer empty ag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
When transmitting
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
Error detection
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
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