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| 型號(hào)： | M30240M1-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 65/125頁(yè) |
| 文件大?。?/td> | 753K |
| 代理商： | M30240M1-XXXFP |
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CONFIDENTIAL
46
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
pending interrupts for a given endpoint. The USB FCU sets the interrupt status bits. The CPU writes a “1” to
clear the corresponding status bit. By writing back the same value it read, the CPU will clear all the existing
interrupts. The CPU must read then write both status registers, writing status register 1 first and status register
2 second to guarantee proper operation.
The suspend interrupt status bit is set if a USB suspend signal is received. If the device is in suspend mode,
the resume interrupt status bit is set when a USB resume signal is received. There is a single interrupt enable
bit for both of suspend and resume interrupts (bit 7 of the interrupt enable register 2).
The USB reset interrupt status bit is set if a USB reset signal is received. When this bit is set, all USB internal
registers is reset to their default values except this bit itself. This bit is cleared by the CPU writing a “0” to it.
When the CPU detects a USB reset interrupt, it needs to re-initialize the USB block in order to accept packets
from the host.
The Over/Underrun status bit is set (applicable to endpoints used for isochronous data transfer), when an
overrun condition occurs in an endpoint (CPU is too slow to unload the data from the FIFO), or when an un-
derrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO).
The USB Function Interrupt (sum of all individual function interrupts) is enabled by setting the corresponding
bit in the Interrupt Control Register of the Interrupt Control Unit.
USB SOF Interrupt
The USB SOF (Start-Of-Frame) interrupt is used to control the transfer of isochronous data. The USB FCU
generates a start-of-frame interrupt when a start-of-frame packet is received. The USB SOF interrupt is en-
abled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit.
USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Both FIFOs support
up to two separate data sets of variable size (except Endpoint 0), and provide the ability of back-to-back trans-
mission and reception. Throughout this specification, the terms “IN FIFO” and “OUT FIFO” refer these FIFOs
associated with the current endpoint.
In the event of a bad transmission/reception, the USB FCU handles all the read/write pointer reversal and data
set management tasks when it is applicable.
IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint’s IN FIFO location specified by the FIFO write pointer, which auto-
matically increments by "1" after a write.
Endpoint 0 IN FIFO Operation:
The CPU writes a “1” to the IN_PKT_RDY bit after it finishes writing a packet of data to the IN FIFO. The USB
FCU clears the IN_PKT_RDY bit after the packet is successfully transmitted to the host (ACK is received from
the host) or the SETUP_END bit of the IN CSR is set to a “1”.
Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = “0”:
MAXP > half of the IN FIFO size: The CPU writes a “1” to IN_PKT_RDY bit after the CPU/DMAC finishes writ-
ing a packet of data to the IN FIFO. The USB FCU clears TX_NOT_EMPTY bit after the packet is successfully
transmitted to the host (ACK is received from the host). The CPU should only write data to the IN FIFO if the
TX_NOT_EMPTY bit of the IN CSR is a “0”.
MAXP <= half of the IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit after the CPU/DMAC finishes
writing a packet of data to the IN FIFO. If only one packet of data is the FIFO TX_NOT_EMPTY bit gets set
to a “1” and the IN_PKT_RDY bit gets clear to a ‘0’. If two packets of data in the FIFO, then the
TX_NOT_EMPTY bit gets set to a “1” and the IN_PKT_RDY bit stays as a “1” (the FIFO can hold up to two
data packets at the same time in this configuration, for back-to-back transmission). The CPU should only write
data to the IN FIFO if the IN_PKT_RDY bit of the IN CSR is a “0”.
Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = “1”:
MAXP > half of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet
size) is written to the IN FIFO by the CPU/DMAC, the USB FCU sets the TX_NOT_EMPTY bit to a “1” auto-
matically. The USB FCU clears the TX_NOT_EMPTY bit after the packet is successfully transmitted to the
host (ACK is received from the host). The CPU should only write data to the IN FIFO if the TX_NOT_EMPTY
bit of the IN CSR is a “0”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30245MC-XXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30245FCGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30260F3VGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M3A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M8A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240M2 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M2-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M3 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M3-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240M4 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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