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CONFIDENTIAL
54
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
The Endpoint 0 CSR (Control & Status Register), shown in Figure 44, contains the control and status infor-
mation of Endpoint 0.
Figure 44:
USB Endpoint 0 CSR
EP0CSR0 (OUT_PKT_RDY):
The USB FCU sets this bit to a “1” upon receiving a valid SETUP/OUT token from the host. The CPU clears this
bit after unloading the FIFO, by way of writing a “1” to EP0CSR6. The CPU does not clear the OUT_PKT_RDY
bit before finishes decoding the host request. If EP0CSR2 (SEND_STALL) needs to be set - the CPU decodes
an invalid or unsupported request - the setting EP0CSR6 = “1” & EP0CSR2 = “1” is done in a same CPU write.
EP0CSR1 (IN_PKT_RDY):
The CPU writes a “1” to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU
clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is
set.
EP0CSR2 (SEND_STALL):
The CPU writes a “1” to this bit if it decodes an invalid or unsupported standard device request from the host.
The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during control transfer
data or status stages) while this bit is set. The CPU writes a “0” to clear this bit.
EP0CSR3 (DATA_END):
For control transfers, the CPU writes a “1” to this bit when it writes (IN data phase) or reads (OUT data phase)
the last packet of data to or from the FIFO. This bit indicates to the USB FCU that the specific amount of data
in the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the
status phase completes, the USB FCU clears this bit. When this bit is set to a “1”, and the host again requests
or sends more data, the USB FCU returns a STALL handshake.
EP0CSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” if the host sends out a larger data packet than the MAXP size, or if during
a data stage a command pipe is sent more data or is requested to return more data than was indicated in the
setup stage (see description for EP0CSR3). The USB FCU returns a STALL handshake for all subsequent
IN/OUT transactions (during data or status stages) while this bit is set. The CPU writes a “0” to clear this bit.
EP0CSR0
OUT_PKT_RDY Flag (bit 0) (Read Only - Write “ 0”)
0: Out packet is not ready
1: Out packet is ready
EP0CSR1
IN_PKT_RDY Bit (bit 1) (Write “ 1” only or Read)
0: In packet is not ready
1: In packet is ready
EP0CSR2
SEND_STALL Bit (bit 2) (Write “ 1” only or Read)
0: No action
1: Stall Endpoint 0 by the CPU
EP0CSR3
DATA_END Bit (bit 3) (Write “ 1” only or Read)
0: No action
1: Last packet of data transferred from/to the FIFO
EP0CSR4
FORCE_STALL Flag (bit 4) (Write “ 0” only or Read)
0: No action
1: Stall Endpoint 0 by the USB FCU
EP0CSR5
SETUP_END flag (bit 5) (Read Only - Write “ 0”)
0: No action
1: Control transfer ended before the specific length of
data is transferred during the data phase
EP0CSR6
SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read “ 0”)
0: No change
1: Clear the OUT_PKT_RDY bit (EP0CSR0)
EP0CSR7
SERVICED_SETUP_END Bit (bit 7) (Write Only - Read “ 0”)
0: No change
1: Clear the STUP_END bit (EP0CSR5)
EP0CSR7
EP0CSR1
EP0CSR6
EP0CSR0
EP0CSR2
EP0CSR3
EP0CSR4
EP0CSR5
Address: 031116
Access:
R/W
Reset
0016
LSB
0
MSB
7