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參數(shù)資料
| 型號： | KSZ8851SNL-BBE-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 22/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL MAC/PHY FOR KSZ8851 |
| 軟件下載： | KSZ8851SNL Linux Driver Linus' GIT Repo View Driver |
| 設計資源： | Zippy2 Schematic BeagleBoard Zippy2 KSZ8851SNL-BBE-EVAL Bill of Materials |
| 特色產(chǎn)品： | Zippy 2 |
| 標準包裝： | 1 |
| 系列： | LinkMD® |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8851SNL |
| 主要屬性： | 1 個端口，100BASE-TX/10BASE-T |
| 次要屬性： | SPI 接口，LinkMD 線纜診斷 |
| 已供物品： | 板，硬件 |
| 產(chǎn)品目錄頁面： | 1114 (CN2011-ZH PDF) |
| 其它名稱： | 576-3602 KSZ8851SNL-BBE-EVL ZIPPY2 |
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Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
29
M9999-083109-2.0
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 10. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Packet Memory
Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Status Word
(see description in RXFHSR register)
2
Byte Count
(see description in RXFHBCR register)
4 - up
Receive Packet Data
(maximum size is 2000)
Table 10. Frame Format for Receive Queue
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851SNL to host processor with generic
bus interface. User can use the default value for most of the receive registers. The following Table 11 describes all
registers which need to be set and used for receiving single or multiple frames.
Register Name[bit](offset)
Description
RXCR1(0x74)
RXCR2(0x76)
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
RXFHSR[15:0](0x7C)
This register (read only) indicates the current received frame header status information.
RXFHBCR[11:0](0x7E)
This register (read only) indicates the current received frame header byte count information.
RXQCR[12:3](0x82)
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enable RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
RXFDPR[14](0x86)
Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
RXDTTR[15:0](0x8C)
To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1 uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851SNL will generate
RX interrupt in ISR[13] and indicate the status in RXQCR[12].
RXDBCTR[15:0](0x8E)
To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851SNL will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
IER[13](0x90)
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
RXFCTR[15:8](0x9C)
Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
RXFCTR[7:0](0x9C)
To program received frame count value. When the number of received frames in RXQ exceeds this
threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851SNL will generate RX interrupt in
ISR[13] and indicate the status in RXQCR[10].
Table 11. Registers Setting for Receive Function Block
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8851SNL-BBE-EVL | 制造商:Micrel Inc 功能描述:BOARD EVAL MAC/PHY FOR KSZ8851 |
| KSZ8851SNL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 Single Ethernet Port + SPI Bus Interface(Lead Free) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8851SNL-EVAL | 制造商:Micrel Inc 功能描述:BOARD EVALUATION FOR KSZ8851SNL |
| KSZ8851SNLI TR | 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with SPI Bus Interface (I-Temp, Lead free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851SNLITR | 制造商:Micrel 功能描述:Ethernet Controller Single Chip 100Mbps |
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