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參數(shù)資料
| 型號： | KSZ8851SNL-BBE-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 15/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL MAC/PHY FOR KSZ8851 |
| 軟件下載： | KSZ8851SNL Linux Driver Linus' GIT Repo View Driver |
| 設(shè)計資源： | Zippy2 Schematic BeagleBoard Zippy2 KSZ8851SNL-BBE-EVAL Bill of Materials |
| 特色產(chǎn)品： | Zippy 2 |
| 標準包裝： | 1 |
| 系列： | LinkMD® |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8851SNL |
| 主要屬性： | 1 個端口，100BASE-TX/10BASE-T |
| 次要屬性： | SPI 接口，LinkMD 線纜診斷 |
| 已供物品： | 板，硬件 |
| 產(chǎn)品目錄頁面： | 1114 (CN2011-ZH PDF) |
| 其它名稱： | 576-3602 KSZ8851SNL-BBE-EVL ZIPPY2 |
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Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
22
M9999-083109-2.0
Clock Generator
The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator
(as described in the pin description).
Serial Peripheral Interface (SPI)
The KSZ8851SNL supports a SPI interface in slave mode. In this mode, a external SPI master device (micro-controller or
CPU) supplies the operating serial clock (SCLK), chip select (CSN) and serial input data (SI) which is clocked in on the
rising edge of SCLK to KSZ8851SNL device. Serial output data (SO) is driven out by the KSZ8851SNL on the falling edge
of SCLK to external SPI master device. The falling edge of CSN is starting the SPI operation and the rising edge of CSN
is ending the SPI operation. The SCLK stays low state when SPI operation is idle. Figure 6 shows the SPI interface
connection for KSZ8851SNL.
Figure 6. SPI Interface to KSZ8851SNL
There are four SPI operations depending on the opcode inside the command phase:
Internal I/O registers read (opcode = 00)
Internal I/O registers write (opcode = 01)
RXQ FIFO read to receive packet (opcode = 10)
TXQ FIFO write to transmit packet (opcode = 11)
As shown in Table 4 and 5, there are two phases in each SPI operation, the first is command phase and the following is
data phase. Command phase is two bytes long for internal I/O registers access and one byte long for TXQ/RXQ FIFOs
access. Data phase on internal I/O registers access is in the range of one to four bytes long depending on the specified
byte enable bits B[3:0] in command phase, and data phase on TXQ or RXQ FIFOs access is limited up to 6 Kbytes for
TXQ access or 12 Kbytes for RXQ access.
Command Phase (SI pin)
Byte 0 [7:0]
Byte 1 [7:0]
SPI
Operation
Opcode Byte enable
Register Address
Don’t care bits
Data Phase
(SO or SI pins)
Internal I/O
Register Read
0 0
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
1 to 4 Bytes
(read data on SO pin)
Internal I/O
Register Write
0 1
B3 B2 B1 B0 A7 A6 A5 A4 A3 A2
X X X X
1 to 4 Bytes
(write data on SI pin)
Note: In Command phase, A[7:2] access register address location in double word and B[3:0] enable which byte to
access during read or write. In Data phase, the byte 0 is first in/out and byte 3 is last in/out during read or write.
B[3:0] -> 1: enable byte, 0: disable byte.
Table 4. SPI Operation for Registers Access
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8851SNL-BBE-EVL | 制造商:Micrel Inc 功能描述:BOARD EVAL MAC/PHY FOR KSZ8851 |
| KSZ8851SNL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 Single Ethernet Port + SPI Bus Interface(Lead Free) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8851SNL-EVAL | 制造商:Micrel Inc 功能描述:BOARD EVALUATION FOR KSZ8851SNL |
| KSZ8851SNLI TR | 功能描述:以太網(wǎng) IC 10/100BT Ethernet MAC + PHY with SPI Bus Interface (I-Temp, Lead free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8851SNLITR | 制造商:Micrel 功能描述:Ethernet Controller Single Chip 100Mbps |
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