參數(shù)資料
型號(hào): KSZ8851SNL-BBE-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 16/80頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL MAC/PHY FOR KSZ8851
軟件下載: KSZ8851SNL Linux Driver
Linus' GIT Repo
View Driver
設(shè)計(jì)資源: Zippy2 Schematic
BeagleBoard Zippy2
KSZ8851SNL-BBE-EVAL Bill of Materials
特色產(chǎn)品: Zippy 2
標(biāo)準(zhǔn)包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851SNL
主要屬性: 1 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: SPI 接口,LinkMD 線纜診斷
已供物品: 板,硬件
產(chǎn)品目錄頁(yè)面: 1114 (CN2011-ZH PDF)
其它名稱(chēng): 576-3602
KSZ8851SNL-BBE-EVL
ZIPPY2
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
23
M9999-083109-2.0
Command Phase (SI pin)
Byte 0 [7:0]
SPI Operation
Opcode
Don’t care bits
Data Phase
(SO or SI pins)
RXQ FIFO Read
(12 KByte)
1 0
X X X X X X
1 to 12 KBytes
(DMA read data on SO pin)
TXQ FIFO Write
(6 KByte)
1 1
X X X X X X
1 to 6 KBytes
(DMA write data on SI pin)
Note: The Start DMA Access bit 3 in RXQCR register must set to “1” before FIFO
read/write commands. This bit must be clear to “0” when DMA operation is finished.
Table 5. SPI Operation for TXQ/RXQ FIFO Access
SPI Internal I/O Registers Access Operation Timing
As shown in Figures 7 and 8 illustrate the SPI internal I/O registers read and write operation timing, the first two command
byte 0/1 contain opcode (00: read command, 01: write command), B[3:0] Byte enable bits to indicate which data byte is
available in data phase (1: byte enable, 0: byte disable) and A[7:2] address bits to access register location. The following
is data phase either 1, 2, 3, or 4 bytes depending on B[3:0] setting.
Figure 7. Internal I/O Register Read Timing
Figure 8. Internal I/O Register Write Timing
SPI TXQ/RXQ FIFOs Access Operation Timing
As shown in Figures 9 and 10 illustrate the SPI TXQ/RXQ FIFOs write and read operation timing, the first command byte
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