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參數(shù)資料
| 型號： | KAB01D100M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Tantalum Conformal-Coated Capacitor; Capacitance: 22uF; Voltage: 10V; Packaging: Tape & Reel |
| 中文描述： | 多芯片封裝存儲器 |
| 文件頁數(shù)： | 15/72頁 |
| 文件大小： | 1378K |
| 代理商： | KAB01D100M |
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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 15 -
MCP MEMORY
SEC Only
NAND FLASH PRODUCT INTRODUCTION
The NAND Flash Memory is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 264 columns. Spare 8 col-
umns are located in 256 to 263 column address. A 264-word data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages
formed by one NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program
and read operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists
of 1024 blocks, and a block is separately erasable by 8K-word unit. It indicates that the bit by bit erase operation is prohibited on
the NAND Flash Memory.
Table 7. Command Sets
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
O
The NAND Flash Memory has addresses multiplexed with lower 8 I/O
′
s. The NAND Flash Memory allows sixteen bit wide data trans-
fer into and out of page registers. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by
maintaining consistency in system board design. Command, address and data are all written through I/O
′
s by bringing WE to low
while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to
multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except Page Program command
and Block Erase command which require two cycles: one cycle for setup and another for execution. The 8M word physical space
requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same three address cycles following required command input. In
Block Erase operation, however, only two row address cycles are used. Device operations are selected by writing specific com-
mands into command register. Table 7 defines the specific commands of the NAND Flash Memory.
Table 8. NOR Flash Operations Table
Operation
CE
R
OE
WE
BYTE
WP/
ACC
A9
A6
A1
A0
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
RESET
Read
word
L
L
H
H
L/H
A9
A6
A1
A0
DQ15
D
OUT
D
OUT
H
byte
L
L
H
L
A9
A6
A1
A0
A-1
High-Z
D
OUT
H
Stand-by
Vcc
R
±
0.3V
X
X
X
(2)
X
X
X
X
High-Z
High-Z
High-Z
(2)
Output Disable
L
H
H
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
H
Reset
X
X
X
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
L
Write
word
L
H
L
H
(4)
A9
A6
A1
A0
D
IN
D
IN
D
IN
H
byte
L
H
L
L
A9
A6
A1
A0
A-1
High-Z
D
IN
H
Enable Block Group
Protect (3)
L
H
L
X
L/H
X
L
H
L
X
X
D
IN
V
ID
Enable Block Group
Unprotect (3)
L
H
L
X
(4)
X
H
H
L
X
X
D
IN
V
ID
Temporary Block
Group
X
X
X
X
(4)
X
X
X
X
X
X
X
V
ID
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