參數(shù)資料
型號(hào): ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 99/150頁
文件大小: 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
99 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.5.3
HcSoftwareReset register (W: A9H)
This register provides a means for software reset of the HC. To reset the HC, the
HCD must write a reset value of F6H to this register. On receiving this reset value,
the HC resets all the HC and OTG registers, except its buffer memory.
Table 74
contains the bit description of the register.
Code (Hex): A9
write only
15.6 HC buffer RAM control registers
15.6.1
HcBufferStatus register (R/W: 2CH/ACH)
The bit allocation of the HcBufferStatus register is given in
Table 75
.
Code (Hex): 2C
read
Code (Hex): AC
write
Table 73:
Bit
15 to 0
HcScratch register: bit description
Symbol
Access
Scratch[15:0]
R/W
Value
0000H
Description
Scratch register value.
Table 74:
Bit
15 to 0
HcSoftwareReset register: bit description
Symbol
Access
ResetValue
[15:0]
Value
0000H
Description
Writing a reset value of F6H causes the HC to
reset all the registers except its buffer memory.
W
Table 75:
Bit
Symbol
HcBufferStatus register: bit allocation
15
14
13
12
11
10
9
8
reserved
PairedPTD
PingPong
0
R
2
INTL_
Active
ISTL1
BufferDone
0
R
1
ISTL1
BufferFull
ISTL0
BufferDone
0
R
0
ISTL0
BufferFull
Reset
Access
Bit
Symbol
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
reserved
ISTL1_
Active
Status
0
R
ISTL0_
Active
Status
0
R
Reset_HW
PingPong
Reg
0
R/W
ATL_Active
Reset
Access
-
-
0
0
0
0
R/W
R/W
R/W
R/W
Table 76:
Bit
15 to 11
10
HcBufferStatus register: bit description
Symbol
-
PairedPTDPingPong
Description
reserved
0
Ping of paired PTD in ATL is active.
1
Pong of paired PTD in ATL is active.
0
The ISTL1 buffer has not yet been read by the HC.
9
ISTL1
BufferDone
1
The ISTL1 buffer has been read by the HC.
0
The ISTL0 buffer has not yet been read by the HC.
8
ISTL0
BufferDone
1
The ISTL0 buffer has been read by the HC.
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