參數(shù)資料
型號(hào): ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 11/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
11 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
H_PSW2
36
G9
O
connects to the external PMOS switch
LOW
switches ON the PMOS providing V
BUS
to the downstream
port
HIGH
switches OFF the PMOS
when not in use, leave this pin open
open-drain output
digital ground
programmable clock output; the default clock frequency is 12 MHz and
can be varied from 3 MHz to 48 MHz
push-pull output
GoodLink LED indicator output; the LED is OFF by default, blinks ON
upon USB traf
fi
c
open-drain output; 4 mA
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01
μ
F
overcurrent sense input for downstream port 2; both the digital and
analog overcurrent inputs can be used for port 2, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the V
DD_5V
pin
overcurrent sensing input for downstream port 1; both the digital and
analog overcurrent inputs can be used for port 1, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the V
DD_5V
pin
crystal input; connected directly to a 12 MHz crystal; when this pin is
connected to an external clock oscillator, leave pin X2 open
crystal output; connected directly to a 12 MHz crystal; when pin X1 is
connected to an external clock oscillator, leave this pin open
to select whether port 1 is operating in the OTG or non-OTG mode;
see
Table 8
input with hysteresis
downstream D
signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareCon
fi
guration register
downstream D+ signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareCon
fi
guration register
input pin for sensing OTG ID; the status of this input pin is re
fl
ected in
the OTGStatus register (bit 0); see
Table 8
input with hysteresis
D
signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareCon
fi
guration register
[3]
D
+
signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareCon
fi
guration register
[3]
DGND
CLKOUT
37
38
G10
F9
-
O
GL
39
F10
O
V
CC
40
E9
-
H_OC2
41
E10
I
H_OC1
42
D9
I
X1
43
D10
AI
X2
44
C9
AO
OTGMODE
45
C10
I
H_DM2
46
B9
AI/O
H_DP2
47
B10
AI/O
ID
48
A10
I
OTG_DM1
49
A9
AI/O
OTG_DP1
50
B8
AI/O
Table 2:
Symbol
[1]
Pin description
continued
Pin
LQFP64
Ball
TFBGA64
Type
[2]
Description
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