參數(shù)資料
型號： ISP1362BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Single-chip Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 29/150頁
文件大?。?/td> 647K
代理商： ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
—
06 January 2004
29 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The interrupt level 2 (OPR group) contains six possible interrupt events (recorded in
the HcInterruptStatus register). When any of these events occurs, the corresponding
bit would be set to logic 1, and if the corresponding bit in the HcInterruptEnable
register is also logic 1, the 6-input OR gate would output logic 1. This output is
combined with the value of MIE (bit 31 of HcInterruptEnable) using the AND
operation and logic 1 output at this AND gate will cause the OPR bit in the
Hc
μ
PInterrupt register to be set to logic 1.
The interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in
the OtgInterrupt register). When any of these events occurs, the corresponding bit
would be set to logic 1, and if the corresponding bit in the OtgInterruptEnable register
is also logic 1, the 11-input OR gate would output logic 1 and cause the OTG_IRQ bit
in the Hc
μ
PInterrupt register to be set to logic 1.
The level 1 interrupts contains 10 possible interrupt events. The Hc
μ
PInterrupt and
Hc
μ
PInterruptEnable registers work in the same way as the HcInterruptStatus and
HcInterruptEnable registers. The output from the 10-input OR gate is connected to a
latch, which is controlled by InterruptPinEnable (the bit 0 of HcHardwareCon
fi
guration
register).
When the software wishes to temporarily disable the interrupt output of the
ISP1362 HC and OTGC, follow this procedure:
1. Set the InterruptPinEnable bit in HcHardwareCon
fi
guration register to logic 1.
2. Clear all bits in the Hc
μ
PInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.
Remark:
The InterruptPinEnable bit in the HcHardwareCon
fi
guration register
controls the latch of the interrupt output. When this bit is set to logic 0, the interrupt
output will remain unchanged, regardless of any operation on the interrupt control
registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal
without clearing the Hc
μ
PInterrupt register, follow this procedure:
1. Make sure that the InterruptPinEnable bit is set to logic 1.
2. Clear all bits in the Hc
μ
PInterruptEnable register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation:
1. Set all bits in the Hc
μ
PInterruptEnable register according to the HCD
requirements.
2. Set the InterruptPinEnable bit to logic 1.
9.7.2
Interrupt in the DC
The registers that control the interrupt generation in the ISP1362 DC are:
DcMode (bit 3)
DcHardwareCon
fi
guration (bits 0 and 1)
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相關代理商/技術參數(shù)
參數(shù)描述
ISP1362BD,118 功能描述:USB 接口集成電路 USB OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362BD,151 功能描述:USB 接口集成電路 USB OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362BD,157 功能描述:USB 接口集成電路 USB OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362BD157 制造商:NXP Semiconductors 功能描述:IC CONTROLLER USB-OTG 64LQFP 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 64-LQFP
ISP1362BDFA 功能描述:IC USB OTG CONTROLLER 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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