參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 93/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
93 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12
ConnectPullDown_DS1
0
disconnect built-in pull-down resistors on
OTG_DM1 and OTG_DP1
1
connect built-in pull-down resistors on OTG_DM1
and OTG_DP1
Remark:
This bit is effective only when port 1 is
con
fi
gured as the host port (the OTGMODE pin is
HIGH, and the ID pin is LOW). When port 1 is
con
fi
gured as the OTG port, (the OTGMODE pin is
LOW), the pull-down resistors on OTG_DM1 and
OTG_DP1 are controlled by the LOC_PULL_DN_DP
and LOC_PULL_DN_DM bits of the OtgControl
register.
0
clock can be stopped when suspended
11
SuspendClkNotStop
1
clock cannot be stopped when suspended
0
use external OC detection; digital input
10
AnalogOCEnable
1
use on-chip OC detection; analog input
0
HC interrupt routed to INT1, DC interrupt routed to
INT2
9
OneINT
1
HC and DC interrupts routed to INT1 only, INT2 is
unused
0
normal operation; DACK1 is used with read and
write signals; power-up value
8
DACKMode
1
reserved
0
HC DMA request and acknowledge routed to
DREQ1 and DACK1, DC DMA request and
acknowledge routed to DREQ2 and DACK2
7
OneDMA
1
HC and DC DMA requests and acknowledges
routed to DREQ1 and DACK1; DREQ2 and DACK2
unused
0
DACK1 is active LOW; power-up value
6
DACKInputPolarity
1
DACK1 is active HIGH
0
DREQ1 is active LOW
5
DREQOutputPolarity
1
DREQ1 is active HIGH; power-up value
01
microprocessor interface data bus width is 16 bits
4 to 3
DataBusWidth[1:0]
Others
reserved
0
INT1 interrupt is active LOW; power-up value
2
InterruptOutputPolarity
1
INT1 interrupt is active HIGH
0
INT1 interrupt is level-triggered; power-up value
1
InterruptPinTrigger
1
INT1 interrupt is edge-triggered
0
power-up value
0
InterruptPinEnable
1
global interrupt pin INT1 is enabled; this bit should
be used with the Hc
μ
PInterruptEnable register to
enable pin INT1
Table 64:
Bit
HcHardwareCon
fi
guration register: bit description
continued
Symbol
Description
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