參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 100/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
100 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.6.2
HcDirectAddressLength register (R/W: 32H/B2H)
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL
or ATL buffers. This register speci
fi
es the starting address of the buffer and byte count
of the data to be addressed. Therefore, it allows the programmer to randomly access
the buffer. The bit allocation of the register is given in
Table 77
.
Code (Hex): 32
read
Code (Hex): B2
write
7
6
-
ISTL1_ActiveStatus
reserved
0
The ISTL1 buffer is not accessed by the slave host.
1
The ISTL1 buffer is accessed by the slave host.
0
The ISTL0 buffer is not accessed by the slave host.
5
ISTL0_ActiveStatus
1
The ISTL0 buffer is accessed by the slave host.
0 to 1
resets internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register
can be read from bit 10 of this register.
4
Reset_HW
PingPong
Reg
1 to 0
has no effect.
0
The HC does not process the ATL buffer.
3
ATL_Active
1
The HC processes the ATL buffer.
0
The HC does not process the INTL buffer.
2
INTL_Active
1
The HC processes the INTL buffer.
0
The HC does not process the ISTL1 buffer.
1
ISTL1BufferFull
1
The HC processes the ISTL1 buffer.
0
The HC does not process the ISTL0 buffer.
0
ISTL0BufferFull
1
The HC processes the ISTL0 buffer.
Table 76:
Bit
HcBufferStatus register: bit description
continued
Symbol
Description
Table 77:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDirectAddressLength register: bit allocation
31
30
29
28
27
26
25
24
DataByteCount[15:8]
0
R/W
20
DataByteCount[7:0]
0
R/W
12
BufferStartAddress[14:8]
0
R/W
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
19
R/W
18
R/W
17
R/W
16
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
11
R/W
10
R/W
9
R/W
8
reserved
0
-
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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